The FPGA Logic Analyzer is a powerful tool in your design verification and debugging arsenal. Using it you can monitor the state of multiple nodes inside the FPGA design. Altium Designer 6.0 includes a new, configurable logic analyzer, that gives you run-time control over which bus or nets are being monitored, and which are being used to trigger off.

The new LAX is a configurable component, supporting 8, 16, 32 or 64 bit capture. It also incorporates an internal multiplexer, using this you can configure the LAX to monitor any number of nets and buses, and then select which set of signals is to be captured while the circuit is under test.

You can also trigger off the external trigger, or define any trigger pattern on any of the available sets of signals.

Altium Designer 6.0 also includes the ability to disassemble your code in real time and to view it in the waveform viewer.