Schematic-Based Declaration

Adding a simple directive to a net at the schematic level will tell the system that this is a member of a differential pair.

The design compiler will look for two nets of the form NetName_N and NetName_P which both have a differential pair directive on them. From this information it will construct a differential pair object to be passed to the board layout system. This happens via an ECO and all differences between the schematic and PCB are detected and reported by the design comparator.

PCB-Level Differential Pair Objects

A new PCB object has been created to represent a differential pair. This is similar to a net class and is simply a named group of two nets. A new differential pair class object has also been added. This allows a group of differential pairs to be easily handled and to have rules applied to them.

Differential Pair Panel

A new mode, Differential Pair Editor, has been added to the PCB panel. This editor provides a view of all differential pair classes, differential pair objects and their individual nets. All these items can be selected and highlighted on the PCB. It also allows easy creation of differential pairs as well as providing access to the Differential Pairs Rule Wizard. Differential pairs can also be created from the main edit menu by selecting the "Place Differential Pairs" command, selecting two nets, and choosing a name.

Differential Pairs Rule Wizard

This wizard automates the process of constructing the various rules that can be used to specify the constraints for a group of differential pairs.

There are three main rules that can be applied to differential pairs. The first two are existing rules and the third is a new rule specifically for working with differential pairs. These rules are used by the interactive differential pair router and the DRC system to validate the differential pair routing.

• Matched Net Length - This allows the specification of the maximum difference in length between nets in a differential pair or a group of differential pairs.
• Routing Width - This allows the specification of the width of the tracks to be used in the differential pair. It includes width by layer and impedance driven width.
• Differential Pairs Routing - This allows a number of parameters to be applied to a group of differential pairs. This includes the minimum, preferred and maximum gap between the two nets within the pair, as well as the maximum uncoupled length.

Interactive Differential Pair Router

The Interactive Differential Pair Router allows the user to pick a net from a differential pair and then route it. The other net within the pair will 'follow' the routing of the first net. The interactive router will maintain the specified routing widths and gaps and also provide tools for changing layers with intelligent use of vias. This also includes Smart Completion that automatically finds paths to finish the routing process.

Graphical Indication of Differential Pairs

Any nets that are part of differential pairs are indicated as such on the PCB.

Integration with FPGA Differential Pairs

Modern FPGAs, even those with very low cost, can have a large number of I/O pins that can be configured as differential pairs.

To make it easy for the user to harness the power of these, Altium Designer includes full support for integration of FPGA-based differential pairs, and the PCB design system.

Essentially this allows a single net at the FPGA level to be assigned to a differential I/O standard, such as LVDS, and for this to be mapped to a pair of physical nets at the PCB design level.

This process is controlled using the FPGA Signal Manager.

The design compiler can also determine if the pins used as differential pairs at the PCB design level map correctly to the allowable pairs on an FPGA device. Signal Integrity Analysis Altium Designer's Signal Integrity analyzer provides full support for the simulation of differential pairs. This uses the correct signal integrity model for pins when using the LVDS standard with FPGAs.