In this video you will see an example of Altium Designer's powerful Signal Integrity features being used to optimize signal drive settings in an FPGA Design. Topics covered include importing IBIS models, simulating reflection characteristics, finding coupled nets, checking for crosstalk and using the termination advisor to select the type of terminator and the best values for the terminator components.

The design used in the video ships with the latest update of Altium Designer, along with a detailed tutorial document: TU0126 Checking Signal Integrity on an FPGA Design.

This example is based on the daughterboard, NBP28. This daughterboard includes a Xilinx Spartan 3, a Sharp LH79520 incorporating an ARM 7 processor, SRAM and Flash RAM.

In this example we are going to answer the question: "how hard can I drive the signals D[31..0] before ringing and crosstalk will prevent correct operation?" Or alternatively: "what is the optimum slew and drive settings to use for FPGA pins driving signals D[31..0]?"