Increasing clock speeds and fast serial interconnections are bringing high-speed design considerations into mainstream board development. High-speed signal propagation places particular demands on the physical design. Altium Designer supports high-speed design with targeted design rules, complete system-level support for managing differential signals, and built-in signal integrity analysis.
Altium Designer’s extensive rules system allows you to create constraints targeted towards high-speed design and differential signaling. For example, you can set the maximum allowable length of nets, control the number of vias in a net and match the lengths of defined nets, automatically adding accordion segments to traces as required. You can also specify the maximum allowable parallel run of traces to avoid crosstalk between nets, and fully-constrain the physical layout of differential signal pairs on your board.
Working with differential signals
Differential signaling is being increasingly used in mainstream board design – particularly where programmable devices are used. FPGA vendors are including extensive LVDS capabilities in even their lower-cost device ranges because it not only improves reflection noise, but also electromagnetic interference (EMI) and power consumption. Altium Designer provides system-wide support for differential signaling, and lets you take full advantage offered by the LVDS capabilities of today’s FPGAs.
You can define differential signal pairs at the schematic or PCB level – Altium Designer will propagate and synchronize the definitions throughout the project. With linked FPGA and PCB projects, Altium Designer automatically maps a differential signal defined as within the FPGA project to appropriate signal pairs in the physical design.
Altium Designer’s PCB editor includes interactive routing support for differential signals, allowing you to simultaneously route both nets of a pair under full design rule compliance. This provides unified, system-wide support for differential signal from FPGA design right through to PCB layout.
Managing signal integrity issues
The fast edge transitions on modern logic families are making signal integrity analysis a crucial part of the physical design process. FPGAs in particular can present significant problems. The wide range of programmable I/O characteristics available on these devices complicates the process of correctly terminating signal lines to prevent excessive reflections.
With Altium Designer you can perform signal integrity analysis at the capture stage, as well as during board layout. This allows you to identify potential problem areas, determine the correct termination strategy and add the necessary components to the design before moving to PCB layout.
Full impedance, signal reflection and crosstalk analysis can be run on your final board to check the real-world performance of your design after layout is complete. Signal integrity screening is built into the Altium Designer design rules system, allowing you to check for potential signal integrity violations as part of the normal board DRC process