Many of today’s high-density FPGA devices come in gridded packaging such as BGAs. It is often extremely difficult or impossible to physically probe pins on these devices to determine signal status during system development. This can make physical debugging of the circuit a difficult challenge.
Altium Designer leverages the JTAG capabilities of FPGAs to allow you to dynamically investigate the status of any pins on the device without the need for physical access to the pins. JTAG boundary scan allows for transparent monitoring of the signal status on the device. When your Altium Designer system is connected to a suitable development board, such as Altium’s device-independent NanoBoard, or your JTAG-equipped prototype or production board, the in-built, real-time JTAG Viewer allows you to easily view the state of all the pins on any JTAG supported component. This forms part of Altium Designer’s interactive FPGA development methodology – LiveDesign.
The JTAG Viewer presents you with a footprint and symbol view of the target device. You can manually capture a snapshot of the pin status of the device, or have the display update dynamically as the circuit operates. You can hide the display of unused pins, and select any single or group of nets within your design to focus on. This allows you to easily monitor the status of just the pins you are interested in.
Pin status can also be dynamically reflected and displayed on the source schematics for your project, and the PCB layout. This allows you to easily trace signals throughout the entire design.
With Altium Designer, you can monitor the status of critical lines in real-time as you exercise the circuit to determine correct state changes, and easily see problems such as stuck signal lines. This ability to easily view the status of the physical pins of an FPGA, or indeed any JTAG device supported by the system, provides a valuable aid in debugging your design at the physical level when working with high pin-count JTAG-enabled devices such as FPGAs.