Protel 98 SP3 installation notes

Service Pack Information

Installation Notes
  • To install the Service Pack run the downloaded file and follow the instructions.
  • Compatible with both the licensed and trial versions of Protel 98.
  • The Service Pack modifies the existing Protel 98 files. Do not uninstall the existing installation of Protel 98 before installing the Service Pack
  • To ensure that Protel 98 is not running before installing the Service Pack we recommend that you restart your machine before beginning the installation.
  • Protel 98 Service Pack 3 is cumulative and includes all previous service packs. You do NOT need to have previous Protel 98 service packs installed before installing Service Pack 3.
Updates and Enhancements

Below is a list of issues addressed in this Protel 98 service pack. All issues addressed by previous service packs are also included in this service pack.

Protel 98 Service Pack 3 updates and enhancements include the following:
  • PCB net analysis is disabled when a net is set to hidden (View-Connections-Hide Net). This was not always occurring, resulting in long delays when working with large nets or many nets (for example when moving components).
  • Polygons that are connected to the same net and overlap (but are on different layers) no longer cause the net analyser to run slowly.
  • Polygon arcs around pads would occasionally be sized incorrectly, causing violations.
  • PCB Designator and Comment strings now default to be visible when the component properties are reset in the Preferences dialog.
  • PCB Designator and Comment strings no longer rotate by 180 degrees when you use the Place Component dialog to place new components on the bottom layer.
  • The component layer can only be toggled with the "L" shortcut key during placement. Using the "+" and "- " shortcut keys has been disabled as this caused problems with the layer association.
  • The information at the bottom of the PCB Violation Details dialog displays correctly.
  • The PCB drill drawing Legend now prints correctly for multiple sheet printouts using the Final print option.
  • Surface mount pads with holes are now included in the drill drawing.
  • The Protel HPGL Plotter driver correctly creates a .PLT file.
  • The Jump Location dialog now remembers the last used coordinates, and only jumps to valid locations within the workspace.
  • The screen updates correctly when moving a single layer PCB object and changing layers.
  • The Make PCB Library add-on builds the library with the correct component reference point and rotation.
  • Pre-routed tracks and vias that are locked and have the correct design rules applied are no longer ripped up by the autorouter (the autorouter will automatically break all track segments at junctions, pads and vias).
  • The autorouter automatically removes duplicate track segments, vias and free pads at the completion of the autorouting process.
  • The Autorouter Setup dialog now supports resizing of columns and horizontal scrolling in the Rules Tab.
  • It is now possible to match by designator and selection during global editing in Schematic.
  • The Document Number and Document Revision fields have been resized in the Organization Tab of the Schematic Document Options Dialog.
  • The Find Schematic Component dialog now displays the component description when a component is clicked on, and the library description when the library is clicked on.
  • The backup folder field in the AutoSave dialog now supports path/folder strings up to 255 characters.
Problems fixed in Protel 98 Service Pack 2
  • Loop removal has been greatly enhanced to now support; partially routed nets, complex loops, incomplete loops, and T-junctions (overlay a track segment on the piece of the T that you want to keep to if you find that it removes the wrong piece).
  • Netlist loading has been enhanced to substantially improve loading time.
  • Accelerator keys were added to the Design Netlist dialog.
  • After selecting Place » Track you would get a DRC violation as you moved the cursor over existing component pads, tracks and vias.
  • Vias and free-pads no longer get dragged with a track when the track end is being moved, unless the track end is at the center of the via or free-pad.
  • Vias that are automatically inserted during manual routing follow the via style defined in the Routing Via Style design rule.
  • PCB vias that are tented (completely masked) are not included in the solder mask Gerber files.
  • The default track width can be changed to any width between the minimum and maximum specified by the appropriate Width Constraint design rule (signal layers only).
  • The default track width can be changed to any width during track placement on a non-signal layer.
  • The following method is used to set the track width when Place » Track is selected: if a non-signal layer then use the default width; if a signal layer then use the default width if it lies within the range specified by the appropriate rule, otherwise use the minimum specified by the rule.
  • When placing a track onto a previously focused track the placed track changed into the look ahead segment.
  • Component comment and designator strings can now be placed on any layer.
  • Designator and comment strings were defaulting to hidden status when loading or forward annotating a netlist.
  • When the Design Rule Checking dialog was opened with the Create Report File check box off, ticking it would not enable the report filename field.
  • A signal layer polygon will not pour over a keep out layer polygon.
  • Polygon pour would sometimes miss tracks.
  • When a polygon overlaps it will not connect to any pads on their net which lies within the other polygon. As a general practice polygons should not overlap, and if they do you should use the remove dead copper option.
  • DXF import and export has been enhanced.
  • Re-optimizing the nets while moving a selection (N shortcut key) could cause an error.
  • Changes to the draw order in the Preferences/Draw Order dialog box is remembered.
  • Place component had incorrect reference point if previous place component involved changing layers.
  • Arcs printed on subsequent pages (not first) were remembered from the previous page.
  • When printing a mirrored layer in Advanced PCB full 360° arcs would not print.
  • PCB printing scale was incorrect when printing more than one page.
  • The Ibmats.PCB template file was missing.
  • Memory leaks during autorouting have been removed. The autorouter would sometimes route power plane nets on the signal layers.
  • The autorouter would sometimes generate a high number of conflicts and producing poor routing results.
  • The autorouter’s maximum pin limit per component has been increased to 5000.
  • Under certain circumstances it was not possible to add library files in the Change Library File List dialog box (both schematic and PCB).
  • An application error could occur when loading files with library components containing WMF graphics.
  • When a Protel Dos schematic was opened all components created with lines were missing.
  • Pressing the Insert button during schematic power object placement (morphing) could cause an exception error.
  • Help menu items in the Schematic Library Editor now work correctly.
  • Reannotating designators in a project and closing all sheets now prompts to save.
  • After deleting parts or components from a schematic library and then closing the library you are now prompted to save.
  • Generating a netlist or running an electrical rules check could give a GPF under the following circumstances. The design includes a port (any name), 2 power ports (different names) and 2 hidden pins (one each with the same name as the power ports). The port and power ports are all connected with a wire.
  • Selecting Tools » Create Symbol from Sheet and selecting the current schematic sheet could cause an access violation.
  • Maximum path length for generating a schematic netlist or ERC report was 97 Characters.
  • If the first part (part 1) of a multi-part schematic component is not used the component will still be included in the Spread format BOM.
  • Panels, dialogs and Editor Tabs have been upgraded to provided better support for large fonts.
  • Duplicate entries were created in the history list of the Run Process dialog box.
  • A minimized document window now restores when selected form the Window menu.
  • Double clicking in the Current List of Symbols in the Text Editor Edit Syntax dialog correctly removes the symbol from the list.
  • Errors could occur when attempting to print with no printers installed.
  • The PLD device catalog now calls the device libraries correctly. The device attributes will display correctly in the Target Device dialog, and the device will compile correctly.
  • Some PLD fitters were not being called automatically.
  • PLD now supports the Xilinx XC9572PLCC44 and the Atmel ATF1508 devices.
Problems fixed in Protel 98 Service Pack 1
  • Using Undo after clearing the netlist in Advanced PCB could cause saved files to contain invalid data. An error would occur when attempting to load the saved PCB file.
  • Client:TileAllOpenDocuments process caused an error when run after closing one of only two open PCB documents.
  • Advanced PCB 98 would print to the default printer, regardless of which printer was selected in the Printer Setup dialog.
  • Floating Point error could occur if the mouse was moved past the right edge of the PCB workspace (at minimum zoom level).
  • When a netlist was generated from a PCB the split plane nets were not separated into individual nets.
  • An access violation sometimes occurred when EDA/Client was closed after re-pouring a PCB polygon.
  • Could not print more than 1 page in Advanced PCB 98 (Windows 95 only).
  • PCB vias that are tented (completely masked) were not removed from the solder mask printout.
  • Gerber files with embedded apertures used imperial measurements for the apertures, regardless of the current board units.
  • Gerber output dialog sometimes reported 'No Apertures Loaded' when apertures were loaded.
  • The autorouter would stop responding if the PCB window was closed during routing.
  • The autorouter sometimes reported an Out of Memory message when routing large boards. When necessary it now utilizes Windows virtual memory.
  • Restarting the autorouter (AutoRoute » Restart) after it had been stopped (AutoRoute » Stop) could cause an exception error.
  • Ability to export HyperLynx files from Advanced PCB 98 (File/Export) has been added.
  • Warning occurs if no keepout area is defined when attempting to AutoRoute a PCB.
  • Ability to add members to a class by double clicking in the 'Object Classes' dialog box has been added in Advanced PCB 98.
  • The library description in the Library Add/Remove dialog box was sometimes incorrect.
  • Schematic project hierarchy was not building correctly if the project was opened automatically when Client was started. This could result in problems with multiple sheet processes such as ERC, netlist and BOM.
  • The Schematic BOM Wizard (Protel BOM format only) was limited to a maximum number of 255 characters in a group, which could result in designators being removed.
  • The appearance and behavior of the icons in the Project Manager has been improved for complex schematic projects.
  • Advanced SIM 98 would not run if installed in a path containing long filenames.
  • MonteCarlo analysis produced an error because the .BIL file was not being read correctly. 30-day Trial version of Advanced PCB could give a floating point error when attempting to drag a component.
  • An exception error could occur when trying to open the spreadsheet Page Setup or Format Pattern dialog boxes.

  • XOR/XNOR formatting error could occur when creating .PLD files from Advanced Schematic.
  • There were problems generating large PLA files from Advanced PLD 98.
  • Signal pins could be assigned to GND/VCC pins in Advanced PLD 98.
  • Memory allocation problems on the PLCC version of the ATV2500B and ATV750B has been corrected in Advanced PLD 98.
  • Polarity problem for export files when the DEMORGAN option is used in Advanced PLD 98 has been corrected.
  • Verification error in the Espresso minimization routine in Advanced PLD 98 has been corrected.
  • Problem with the $DEFINE parsing when distinguishing between THIS and THISTOO in Advanced PLD 98 has been corrected.
  • Advanced PLD 98 XNF generation has been updated to be compliant with the M1 tool set.
  • PLD device libraries have been updated.
  • PLD virtual designs can now contain 500 pins and 500 internal nodes (up from 200).
  • Advanced PLD 98 now supports C-style comments. // This is a comment
  • Advanced PLD 98, the number of nested repeats has been updated to 64K.
  • Advanced PLD 98 file cache has been increased from 1K to 16K, increasing the speed of large design parsing.
  • Advanced PLD 98 now adds functional test vectors to the JEDEC file when a simulation is run and the JEDEC file exists.
  • Tab key in TexEdit Server did not insert space characters.
  • Cursor was clipped when typing text to the far right edge of the window in the TextEdit server.
  • The Macro server did not run properly if the following system file could not be found, Vcl30.dpl.
  • Most help files have been updated and revised to enhance the Index and the Find features.
  • The following file types are now registered with the Windows registry and associated with EDA/Client 98 - PCB, SCH, RCS, LIB.
  • A memory leakage sometimes occurred when switching between documents of different types.