The advent of low-cost, high-capacity, high-performance field programmable gate arrays (FPGAs) has changed the way designers can look at the process of electronic systems design. FPGAs extend the concept of programming device intelligence from software alone to encompass both software and hardware. With this approach, the system hardware itself – from mass logic to high-performance microprocessors and system memory – can be defined in the ‘soft’ realm, allowing designers to create complete systems within the programmable fabric of an FPGA.
By folding hardware design into the soft, programmable realm, designers can use an iterative approach that allows experimentation with ‘what if’ scenarios, without increasing design times. The results are downloaded into reprogrammable devices so they can be evaluated within a rapid prototyping environment, allowing designers to explore different implementations before committing to a specific hardware solution.
Just as important, the opportunity also exists for designers to evaluate their designs in terms of user experience instead of as a collection of features and benefits. Using a reconfigurable FPGA development board, they could interact with the system under development using real data and devices, to literally gain the end user’s perspective. Designers would be creating working systems without the need for traditional, multiple prototyping steps.
This is the potential of an FPGA-based development workflow to accelerate the design process and reintroduce an intuitive, hands-on design style. Unfortunately, traditional FPGA design tools stand in the way of unlocking this potential.
Stuck in the ASIC design cycle
Traditional FPGA design methodology evolved from the ASIC design process. In this approach, design verification takes place entirely in simulation using stimulus files to represent real-world input and abstract waveforms for output. The designer can never fully interact with and validate the design until it is fabricated as a prototype. This approach has no means to capitalize on an FPGA’s potential to allow designers to simply build and test designs in hardware, repeatedly.
In the traditional process, additional development time must be allocated for multiple prototyping steps to fully debug designs. Each prototype cycle may take weeks or months, which has become an unacceptable delay in today’s marketplaces. Furthermore, the traditional emphasis is on getting the prototype bug-free – that is, in agreement with simulation results – as opposed to making it the optimal product for the end user.
The traditional development process actually hinders the ability to innovate for FPGA and systems designers. Conventional design flows, especially those based on embedded design tools from FPGA vendors, are composed of a collection of separate and isolated design tools. As each task is completed, the designer must transfer the resulting design data to the next tool, and manually ensure that changes made within one design tool are reflected in other design databases. The sheer effort (and risk, and time) involved in this sequential design process prohibits exploration of alternative design options.
A high-level approach opens up FPGA potential
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| The full potential of FPGAs can be harnessed when embedded hardware development, physical hardware design and software development all exist in a single, fundamentally-connected design environment. |
For designers to unlock the potential of hands-on design with FPGAs, they first need a design system that unifies the design flow and allows them to program and test their ideas within an FPGA as quickly and easily as possible. Such a ‘holistic’ design system would use a single application and single pool of design data for the entire process. A change in one design domain would update the same data files being used by other domains.
If that system was unified from the ground-up, the abstraction of the design process could be raised to a point at which the design’s intellectual property (IP) is not tied to particular physical hardware devices, microprocessors or even proprietary IP cores. The system would apply interfacing layers to isolate the device intelligence that determines design functionality and competitive value from underlying hardware platform and devices. With the design environment then handling lower-level complexity, designers of any discipline (hardware, software or FPGA) could simply select and connect design elements using a schematic or graphical design entry system and library-based, royalty-free processor, peripheral memory and functional block IP.
A reconfigurable hardware development platform built around a high-performance, high-capacity FPGA is necessary to complete this high-level design process. The development board would need to be ‘smart’ enough to communicate with the design system at a high level, in real time. That way, a designer can load a design into an FPGA connected to real hardware, test it using virtual test instruments and then quickly revise and revalidate the design, all in a single unified design environment.
Such a holistic design system would form the foundation for the unified methodology with the speed and flexibility to support hands-on prototyping and exploration. The designer could then approach the design from the customer’s point of view, rather than having to first make a decision about the physical hardware configuration before understanding exactly how the product should operate in the real world.
The system manages the details
A unified design system that supports familiar high-level design paradigms at a native level can effectively hide the underlying complexity of the hardware. The designer is free to focus on the essence of the product’s development – its functional soft intelligence – and trust that the system is managing all implementation details.
For example, in a traditional design flow, the designer has to define FPGA pin connections to the board, manually entering pin configurations into a text file or spreadsheet. Any change to the FPGA or board design requires the designer to return to the file and modify its contents by hand. In a holistic process, the designer can simply drag and drop pre-configured, plug-in components straight from the design system’s component libraries, and the system keeps track of pin assignments automatically.
A high-level design approach makes designs easier to assemble and modify from the system-level perspective through several levels of design abstraction. First, it would offer IP libraries with functional blocks and components – microprocessors, peripherals and memory – that are pre-synthesized and verified to suit the architecture of all supported FPGA devices. These ready-to-go blocks of circuitry remove the need to worry about the underlying device architecture, allowing a designer to select the proper programmable device to suit the system under development, rather than the other way around.
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Flexible SoC systems, including external |
IP libraries would offer ready-to-use IP for connectivity options, such as USB or Ethernet ports, where the elements from all domains – hardware, software and embedded hardware – are included. These typify ‘commodity’ functions that add little unique value to the design, so the ability to just drop them into the design frees designers to concentrate on developing innovative features that will deliver competitive value.
To simplify the high-level design process, the Wishbone open-system bus interconnect standard can be used to ‘normalize’ the interfaces between processors, peripherals and memory. The standard’s library-based interface cores ‘wrap’ around predefined processors and peripherals, providing an isolating layer between the existing interface arrangement and a hardware Wishbone bus. The designer can then replace a processor or peripheral component without disrupting the rest of the design, or even needing to know about the low-level hardware architecture. This ease of use promotes design exploration and experimentation.
This concept would also extend to the software layers that connect the
hardware to the application software. Built-in interface layers and drivers can
be inserted to automatically manage the interfacing details, much like an
application programming interface (
Smart development board brings design to life
Adding a smart, reconfigurable hardware development board to this high-level design approach brings the soft device intelligence to life in FPGAs running on the designer’s bench. The hardware development board and design system would work together in a unified design environment to give the designer the visibility and I/O functionality to fully evaluate the design.
| Altium's smart FPGA-based development board - the NanoBoard 3000. Click for a larger view. |
To see and manipulate what’s going on in the FPGA, the design system would intelligently include circuitry needed to insert control and observability into the design. The resulting ‘virtual test instruments’ would provide real-time control and monitoring for exercising and validation. The designer can then quickly employ signal generators, logic analyzers, frequency counters and other tools to examine and change the signals within the FPGA design. Best of all, the instruments would be interacting with a real FPGA implementation, in real time, on the bench. The designer controls the instruments using graphical dashboards in the design software.
Working with a smart reconfigurable hardware development platform, designers can update both the hardware and software at any time, disconnected from the constraints of a predetermined processor or FPGA architecture. The opportunity also exists for designers to directly and easily translate their designs proven in this environment into the final product. A product could be deployed using development platform itself (installed in an off-the-shelf modular enclosure) eliminating the need to go through a full manufacture cycle. Alternatively, designers could directly translate their designs into traditional custom-built PCBs using the same development board circuitry, and the unified design system.
Renaissance of hands-on design
This fast, flexible, hands-on approach stems from turning the traditional design process inside out by focusing first and foremost on the soft design intelligence that defines the product. Hardware engineers can focus on designing unique IP because the hardware is now just as flexible as the software. The high-level design tools help software engineers with only a basic understanding of hardware architecture to define and debug complete products. The smart reconfigurable hardware development platform unifies the crucial implementation, debug and update phase of development with the freedom to experiment with a range of devices, and the ability to easily swap I/O hardware in and out.
Given the design system to support this workflow, designers can use rapid prototyping to develop the product’s end-user experience in the same amount of time that traditionally would be spent chasing down datasheets. This high-level, unified design environment would mean no more sacrificing design innovation to an outdated sequential design process. Designers can focus once again on hands-on design of an optimal product.
