Power consumption constraints have probably compromised more product design plans than any other factor. When a promising concept is in development, balancing that design’s great new functional goals against the sobering facts of power efficiency is often the elephant in the room. It’s very likely to force a number of uncomfortable concessions in the design’s performance or functionality, but managing a design’s power budget is inescapably crucial to its success.
Controlling, and ideally reducing, the power demand of an electronics design has benefits that flow through the entire product development process. It can change a previously unfeasible product design into one that is ready for market, but it also has profound implications in terms of cost and a product’s physical construction. For example, a more power efficient design requires a smaller power supply, fewer components and a smaller enclosure, which reduces the design complexity and the overall cost of the product.
Beyond those direct implications, a design that consumes less power has a simpler and less expensive thermal solution. Reducing or eliminating the need for heat sinks, forced air cooling and airflow paths within the enclosure all serve to benefit the final product. There is also a crucial reliability advantage in maintaining device temperatures within defined limits. Device operating temperature has a direct relationship to its working performance and lifespan, so the emphasis on power management is particularly important in high performance product designs. And these factors can’t be fully resolved until a design reaches the prototype stage.
Creating an electronic design that meets power budgets is a problem that involves all players in the product development process. Systems designers, software developers, embedded hardware experts and board layout specialists all need to consider the tools and methods they use to meet today’s power efficiency goals, and those in the future. The latest technologies, design processes and market trends have introduced new challenges for designers, and the product development systems we use need to respond to this need.
A new predicament
Managing power consumption in electronics designs is not a new problem, but the game is changing as product designs generally shrink in size, and portable products become ubiquitous. Compact battery power, small and complex designs constrained by intimate enclosures, and high-performance devices all serve to challenge a design team’s ability to meet power budgets.
Adding to this complex mix is the increasingly mainstream adoption of programmable devices such as FPGAs. A unique and unprecedented characteristic presented by programmable devices is undefined power consumption. Unlike traditional devices where the internal function and power requirements are predefined, predicting how much supply current an FPGA will need is no longer a simple job of reading the numbers from data sheets. In fact, it will be largely determined by the size and type of design you program into the fabric of the FPGA.
The challenge of managing power consumption in embedded FPGA designs is therefore as unique as the devices themselves. Because an FPGA’s power demands are largely defined by the design programmed into it, the device power figures can only be predicted by tools that take into account the embedded design itself. The alternative is to wait until a prototype has been constructed, test the ‘real’ power consumption, then revise the design in an effort to meet power budgets and performance goals. In practice, the delays this approach introduces into a conventional product development flow would be intolerable.
Nevertheless, FPGAs offer a unique level of design flexibility and are in many ways narrowing the performance gap to their ASIC counterparts, so they are an attractive proposition for today’s product designs. But the variable nature of the device power efficiency and its analysis remains a major challenge for design teams. A look at the power consumption factors in FPGA devices goes some way to explain the complexities in managing and predicting realistic power profiles.
FPGA power analysis
FPGAs redefine power calculations
One unique aspect of conventional volatile FPGAs is the current consumption surge during the initial programming stage that occurs at system power-up, or when the device emerges from a sleep or standby mode. This must be allowed for in the design’s power infrastructure, and during development, it needs to be balanced against the potential efficiency savings delivered by including low power modes. When the mode is changed and the device shut down, the volatile device must be reprogrammed – coincident with a peak in the power consumed – to restore operation.
Adding control functions that shut off all or parts of the embedded hardware may hold the promise of substantial power savings, but the practical reality of that efficiency gain needs to be reasonably predicted by the power analysis tools.
By far the biggest variable in FPGA power consumption is dynamic power, which represents the energy consumed by active switching events. From the contribution of clock signals to I/O lines, dynamic power is largely defined by the design programmed into the FPGA, which of course will change frequently during the course of the product development. The energy is consumed when a change in logic level charges the inherent capacitance presented by the device CMOS junctions.
Dynamic power consumption is therefore a function of frequency, capacitance and voltage (fCV2), so from a design perspective, lowering clock frequencies and supply voltages will deliver power efficiency benefits. Moving to multi-processor design configurations, paralleled low power processing, serial data pipelines, adaptive clock frequencies and other power efficient techniques all serve to reduce the consumed power. The prospect of dynamic reconfiguration to create optimized power modes – where an FPGA is automatically reprogrammed to that alternative mode – is also attractive, but again, the power prediction tools need to confirm that the added complexity incurred by these approaches will be worthwhile.
Static power in FPGAs, by contrast, is relatively consistent and predictable. It also represents one the biggest challenges for FPGA developers as the process technologies are pushed below 90nm. As the physical dimensions of the CMOS architecture drop, the shorter channel lengths and thinner gate oxides allow current to leak across the junctions more easily. FPGA static current consumption therefore increases with each step in process technology, but is partly offset by the low supply voltage of the newer devices. This represents a future challenge for FPGA designers, and in particular those who would like to reap the flexibility and processing power benefits of FPGAs in portable product designs.
The relationship between the major sources of power consumption in FPGAs is nonetheless complex and interactive. An increase in dynamic power – say from a higher clock frequency – will tend to push up the device temperature, which in turn promotes junction leakage and a higher static power. The result can be a condition not unlike thermal runaway, where the higher static power dissipation in the device induces even higher junction leakage, and so on. It’s yet another complication for the FPGA power estimation process.
Available tools
In many ways the task of managing power consumption in embedded FPGA designs is as unique as the devices themselves. Because an FPGA’s power demands are mostly defined by the design programmed into it, the device power figures must be derived by analyzing the embedded design itself.
To cater for this part of the process, the FPGA development tools supplied by the device vendors include power estimation and prediction functions. While still evolving, these systems take into account the parameters of the FPGA device, including its thermal model, and use information from your design to predict the power profile in the selected vendor’s device. In the early prediction stage of the process you might enter basic information such as system clock frequencies and the number of function blocks in use, while a more final estimation of the power consumption can be derived from your design netlist.
In practice this only provides a power profile for that particular embedded FPGA design, which means that the process must be rerun when the proposed design or type of device is changed. Making power efficiency comparisons between design options or devices is therefore a protracted process, and due to the partisan nature of the tools, does not support a choice of FPGAs from different vendors. There is no quick or easy way to dynamically ‘tune’ the FPGA power consumption to satisfy your design goals.
The current state of managing power in FPGA design exists as a predictive process that is ultimately confirmed during prototype testing and subsequent revisions. Changing to a different type of FPGA device to overcome a power consumption issue, while still achieving design goals, is currently a risky option. The time required to reengineer the design to the new target device would push the development past critical deadlines, which is indeed the case for any major change in the embedded hardware design or the device it resides on.
If you rely solely on the available power prediction tools when developing a product design, the hardware (and to some degree the embedded hardware design) must be defined at the beginning of the design cycle. The ability to iteratively explore power saving options during the development cycle is severely limited as a result. Potential options have to be fully and reliably investigated in the early stages of the design process, which places a heavy emphasis on the predictive capabilities of the FPGA power management tools.
Real power analysis and tuning, in real time
The bottom line is that to successfully meet an FPGA design’s power budget without significant design compromises, the predictive power analysis tools you use need all the help they can get. More information is needed though the course of the development process, so that the best design decisions can be made before any prototypes are built.
And from a final product perspective, FPGA power consumption is only part of the story. Power analysis and testing also needs to extend to the surrounding peripheral circuitry and support devices, so that these can also be iteratively developed towards the power efficiency goals.
A broader, more real-time approach to FPGA design can meet these needs and provide a whole new way of optimizing designs within deadlines. For a start, consider an FPGA development board that features live power monitoring through a series of built-in current sensors that report back to the design software.
Power monitoring can be an integral part of the development board's interface panel.
Readings are displayed and logged for both the FPGA and peripheral plug-in boards.
With this approach, the real-time power conditions of the design can be monitored, graphed and logged. Both embedded hardware and software options can now be easily explored, because power saving modes can be accurately analyzed, including the surge effects of reprogramming, and a raft of other power saving techniques fleshed out in real time.
Prediction can give way to quantified results.
The next step is where the complete product development system – encompassing both the development board and design software – is also independent of FPGA vendor and device. This requires a development board that features plug-in FPGA devices cards that can be easily swapped, and this change reported back to the design software. The software in turn supports a wide range of FPGA devices through a system of driver configuration files, and backs this compatibility with libraries of pre-verified and synthesized IP blocks for all supported devices.
A flexible, vendor-independent development board
with plug-in modules and built-in power monitoring.
It directly communicates with the design software.
If this software system also incorporates embedded design capture systems that offer a high level of design abstraction, such as schematic or graphical flow interfaces, iteratively working with embedded designs becomes even easier. Embedded design options can be quickly developed or modified, FPGA devices changed, and the effect on power consumption monitored in real time on the advanced development board.
That board can also include plug-in peripheral hardware sub boards – which also include ‘smart’ power sensors – allowing a full hardware implementation to be analyzed from a functional and power efficiency perspective.
What’s more, consider the product design implications if that development board, or physical variations of it, reflected a realistic product deployment option – or in simple terms, the development board is the product. The path from design to prototype is effectively instant, so the need for predictive tools (power, code and circuit simulation) is vastly reduced. That design ‘sandpit’ would then represent the product design prototype and beyond, allowing the power efficiency of the design to be accurately developed in real time throughout the product development process.
With this approach you are effectively developing your design on the final product, which would ultimately be deployed on matching off-the-shelf hardware or on a custom-built board that supports the same circuitry. Such a system no longer relies on the predicative accuracy of conventional power management tools, allows you to quickly port the design to different FPGA devices, and lets you capture and explore embedded design options quickly.
Armed for the future
Harnessing the full benefits of FPGAs in today’s designs, and in particular those that are battery powered, means understanding and controlling the complexities of FPGA power consumption.
The device vendors are responding to the need for low power FPGAs by introducing new technologies such as non-volatile flash-based devices, power-efficient architecture and advanced power saving modes. Nevertheless, developing FPGA-based product designs will always involve tradeoffs between power efficiency and the design’s functional performance. And that means using the right tools and techniques to realistically balance design choices against the corresponding power consumption penalties, or benefits.
What’s needed for today’s designs, and particularly those in the future, is a flexible and practical approach to solving the power efficiency balance in FPGA designs through real and rapid prototyping. It’s one that does not solely rely on predictive power analysis and estimation tools, but adopts a broader technique by introducing advanced design systems and real time development on real hardware. Designers are then free to explore innovative design options that harness the full benefits of FPGAs for the next generation of energy-efficient products.
