Full listing of SP2 for Altium Designer
FPGA Hardware Design
Verilog® Support 
Service Pack 2 upgrades the DXP™ 2004 system to support Verilog® files for FPGA design. You can create Verilog® files in the text editor, with full syntax highlighting support, and parse and compile the files. The internal DXP synthesis and simulation engines will not be upgraded at this stage to support Verilog®, but full Verilog® design flows can be achieved by selecting supported external synthesis and simulation engines from within the DXP environment.
Intelligent hierarchy for HDL designs
When an FPGA project includes VHDL and/or Verilog® in the design the system will automatically determine the order and hierarchy of HDL files when the project is compiled, and reflect the hierarchy of nested HDL files in the Projects panel.
Actel ProASIC Plus™ support
Support has been added to for the Actel® ProASIC Plus™ family of FPGA devices. The ProASIC Plus™ devices are Flash based, meaning no configuration device is needed. This allows the development of applications that are instantly on at power up, and makes the IP within the FPGA more secure.
Altera® Stratix™ GX support
Support has been added for the Altera® Stratix™ GX family of FPGA devices. The Stratix™ GX FPGA technology is built upon the Stratix™ architecture, and offers a 1.5V logic array and is ideal for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications.
Altera® Stratix™ II support
Pin and gate swapping and PCB ratsnest optimization support has been added for the Altera® Stratix™ II family of FPGA devices. Note: Full process flow and device programming will be supported in future updates.
Xilinx® Virtex-4® support
Pin and gate swapping and PCB ratsnest optimization support has been added for the Xilinx® Virtex-4® family of FPGA devices. Note: Full process flow and device programming will be supported in future updates.
Core resource usage
Information about the amount of FPGA resources that each core will consume is now available. The information is provided for each target FPGA supported by the environment.
New FPGA Examples
Over 30 new examples have been added that demonstrate the use of the new TSK3000A, TSK52 and TSK80 processors, in combination with the other new Wishbone interface and peripheral components, including the Interconnect, the Dual Master, the RAM Controller, the EMAC, the VGA Controller, the SPI controller, and others.
Improved third-party synthesis support 
As well as including an inbuilt VHDL synthesis engine, you can also select the Synplicity®, Xilinx® XST and Altera® synthesizers for FPGA design processing. In Service Pack 2, interaction with these third-party synthesis engines has been enhanced to expose more options from within the DXP 2004 environment, greatly streamlining design processing when using these engines.
Improved simulation Waveform Viewer
The built-in digital Waveform Viewer is used to display HDL simulation results, and also to display outputs from the Logic Analyzer virtual instrument. The Viewer has been updated to enhance usability and provide a better display interface - it now remembers settings, signal and display formatting between sessions. Other enhancements include a new Print Preview feature, and the ability to copy waveforms to the Clipboard for pasting into other applications.
Editing signal names
Signal names can now be edited directly in the Logic Analyzer Waveform document by clicking on the signal name. Also double click will popup the Row Properties dialog.
Extending Positive and Negative Edges
Two new commands have been added to the Right Click menu of the HDL Waveform Editor, Extend Positive Edges and Extend Negative Edges.
Panning support in Waveform editor
Right click and drag is now implemented in the HDL Wave editor.
Nanoboard-NB1 Flash Memory downloading enhancements
When downloading a file to the flash memory on the Nanoboard-NB1
- hex files are converted from ASCII format to binary format
- files can be downloaded to a specified location on the memory
FPGA differential signalling support
FPGA differential signalling is now supported, including synthesis, PCB/FPGA synchronisation and Signal Integrity.
FPGA Generic updates
Generic memory cores have been added to the FPGA Generic.IntLib.
Generic component usage report
After every successful compile of a FPGA Project, an estimate of the generic component usage is displayed in the Output panel. It also includes a list of black-boxes in the design.
Browsing Physical Devices
'Browse Physical Devices' command has been added to the Tools menu in the Devices Page. This gives easy access to the Browse Physical Devices dialog.
Other Updates
- You are now prompted to save a new FPGA or CORE project before compiling. Applies to VHDL and Verilog® documents.
- Xilinx® dual port memory core generation now properly optimizes the selection of RAM blocks. This problem only occurred when memory depths were not a power of two.
- VHDL Simulation Tool folder and SDF Instance Path are now properly remembered.
- Run to time option in VHDL simulation now correctly initializes values when run with the waveform window.
- Constraints on 'bus' ports are now recognized and generated correctly.