The Altium Library Development Center operates under strict procedures designed to ensure the quality and integrity of all libraries and the components they contain.

PCB Footprints - Surface Mount

PCB footprints for surface mount packages are built to the current standards developed by IPC - "Association Connecting Electronics Industries". IPC claims that these land patterns are transparent to the manufacturing process but recommends that they should be optimized to suit the soldering type (wave, reflow) and assembly (components mounted on one or both sides of the board, etc).

Land patterns for BGA devices follow the assumptions found in standard, IPC-SM-782A, Amendment 2 (April 1999). The pads for this standard are defined by the etched copper, rather than by the solder mask.

Land patterns for other surface mount components follow the assumptions found in standard, IPC-SM-782A, Amendment 1 (October 1996).

Metrication

All PCB footprint dimensions are given in metric units. Hard metric dimensions are employed in accordance with the JEDEC JC-11 "Metrication Policy", SPP-003B (February 1998). Departures to this policy are made for some silkscreen dimensions and critical dimensions such as pitch and row spacing.

Footprint Acronyms

A unique name is assigned to each footprint. The naming convention is in sympathy with the IPC component names and the JEDEC Standard, JESD30-B, "Descriptive Designation System for Semiconductor-Device Packages" (April 1995).

View Footprint Naming Convention
(pdf - 263KB)

Schematic - Pin Names

As a general rule pins are assigned the same name as provided in the manufacturers datasheet. For some smaller components it is prudent to use an abbreviation if the pin name is lengthy, in order to provide a clean-looking symbol, eg. AUX for Auxiliary. However different manufacturers regularly use different abbreviations for the same name or use the same abbreviation for different names. On occasions, these inconsistencies appear within the datasheets of the same manufacturer. For example, GND and GRD for Ground. In order to provide a consistency to schematic symbols, a table of abbreviations for over 600 names has been compiled using popular abbreviations employed by a number of manufacturers and appendix A of the "IEEE Standard for Logic Circuit Diagrams" ANSI/IEEE Std 991 - 1986.

View Pin Abbreviation List
(pdf - 44KB)

Class Designation Letter

Default designators are assigned in accordance with Section 22 of IEEE Std 315-1975 (Reaff 1993) "Graphic Symbols for Electrical and Electronic Diagrams".

Graphic Symbols - Normal Mode

Logic diagrams for gates and buffers/drivers are drawn using the time-honored, distinctive-shape logic symbols as prescribed in appendix A of IEEE Std 91.

Simple devices, such as transistors and amplifiers, are drawn according to IEEE Std 315-1975 (Reaff 1993), "Standard Graphic Symbols for Electrical and Electronics Diagrams" and its supplement, IEEE Std 315A-1986.

The pin configuration for remaining components follows the layout presented in the application schematics or the function block diagram of the component. Additional in-house conventions have been refined to standardise the presentation of common components.