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    Complete Environment for Schematic + Layout

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    Entry Level, Professional PCB Design Tool

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    Community Based PCB Design Tool

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    Agile PCB Design For Teams

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    World-Renowned Technology for Embedded Systems Development

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    Intelligent Parts Database for Achieving Realizable Design

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    Extensive, Easy-to-Use Component Database

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    Parametric Search & Navigation of Product Data in Oracle/Agile - PLM

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  • Altium Designer 17

    Stress-free, Native 3D™ PCB design for professionals

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    Altera MAX 7000AE

    Updated: Dec 30, 2013
    Access and use Altera MAX 7000AE CPLD devices in your designs. MAX 7000AE devices are high-density, high performance devices based on Altera’s second generation MAX architecture. The EEPROM based devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates and counter speeds of up to 227.3 MHz. Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).

    Altera MAX 7000B

    Updated: Dec 30, 2013
    Access and use Altera MAX 7000B CPLD devices in your designs. MAX 7000B devices are high-density, high performance devices based on Altera’s second generation MAX architecture. The EEPROM-based devices operate with a 2.5-V supply voltage and provide 600 to 10,000 usable gates and counter speeds up to 303.0 MHz. Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).

    Altera MAX 7000S

    Updated: Dec 30, 2013
    Access and use Altera MAX 7000S In-System Programmable CPLD devices in your designs. The MAX 7000S family of high-density, high performance PLDs is based on Altera’s second generation MAX architecture. The EEPROM-based devices operate with a 5V supply voltage and provide 600 to 5,000 usable gates and counter speeds of up to 175.4 MHz. Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).

    Altera MAX II

    Updated: Dec 30, 2013
    Access and use Altera MAX II CPLD devices in your designs. MAX II devices are low-cost CPLDs containing low power process technology, delivering twice the performance of previous MAX devices. With an on-chip regulator accepting 1.8-3.3V of power supply, it can support clock frequencies of up to 300 MHz. Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).

    Altera MAX V

    Updated: Dec 30, 2013
    Access and use Altera Max V FPGA devices in your designs. MAX V devices feature on-chip flash storage, internal oscillator, and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX V CPLDs can help you meet your low power design requirement. Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).

    Altera Stratix

    Updated: Dec 30, 2013
    Access and use Altera Stratix FPGA devices in your designs. The Stratix family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).

    Altera Stratix GX

    Updated: Dec 30, 2013
    Access and use Altera Stratix GX FPGA devices in your designs. The Stratix GX FPGA technology is built upon the Stratix architecture, and offers a 1.5-V logic array with unmatched performance, flexibility, and time-to-market capabilities. This scalable, high-performance architecture makes Stratix GX devices ideal for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications. Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).

    Altera Stratix II

    Updated: Dec 30, 2013
    Access and use Altera Stratix II FPGA devices in your designs. The Stratix II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).

    Altera Stratix II GX

    Updated: Dec 30, 2013
    Access and use Altera Stratix II GX FPGA devices in your designs. The Stratix II GX FPGA technology is built on the Stratix II architecture and offers a 1.2-V logic array with unmatched performance, flexibility and time-to-market capabilities. This scalable, high-performance architecture makes Stratix II GX devices ideal for high-speed backplane interface, chip-to-chip and communications protocol-bridging applications. Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).

    Altera Stratix III

    Updated: Dec 30, 2013
    Access and use Altera Stratix III FPGA devices in your designs. The Stratix III FPGA family is based on 65-nm and combines lower power with higher performance and density. This scalable, high-performance architecture makes Stratix III devices ideal for next-generation base stations, network infrastructure and advanced imaging equipment. Specific device support and detailed information thereof, can be accessed from the Browse Physical Devices dialog, accessed from the Tools menu in the Devices view (View»Devices View).
    
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