Parent page: Laying Out Your PCB
High-speed printed circuit board design is a process of balancing the circuit design requirements, device technologies, and fabrication materials and methodologies, to deliver a PCB that can transfer signals between the components, with integrity.
The process of routing a board with high-speed signals requires you to manage:
Early in the design process, it is important to identify signals that might require impedance matching so that additional termination components can be included before the component placement process is complete. Since output pins are typically low impedance and input pins are typically high impedance, termination components may need to be added to the design to achieve impedance matching.
Altium Designer includes a signal integrity simulator that can be accessed during both the design capture and board layout phases of the design process, allowing both pre- and post-layout signal integrity analysis to be performed (Tools » Signal Integrity). The signal integrity simulator models the behavior of the routed board by using the calculated characteristic impedance of the traces combined with I/O buffer macro-model information as input for the simulations. The simulator is based on a Fast Reflection and Crosstalk Simulator, which produces very accurate simulations using industry-proven algorithms.
Because both design capture and board design use an integrated component system that links schematic symbols to relevant PCB footprints, SPICE simulation models and signal integrity macro-models, signal integrity analysis can be run at the schematic capture stage prior to the creation of the board design. When no board design is present, the tool allows you to set up the physical characteristics of the design, such as the desired characteristic trace impedance, from within the signal integrity simulator. At this pre-layout stage of the design process, the signal integrity simulator cannot determine the actual length of particular connections so it uses a user-definable average connection length to make its transmission line calculations. By carefully choosing this default length to reflect the dimensions of the intended board, you can gain a fairly accurate picture of the likely signal integrity performance of the design.
Nets with potential reflection problems can be identified and any additional termination components can be added to the schematic before proceeding to board layout. The values of these components can then be further tuned once the post-layout signal integrity analysis has been performed.
► Learn more about Impedance Matching the Components
High-speed design is the art of managing the flow of energy from one point on a circuit board to another point. As the designer, you need to be able to focus your attention and apply the design constraints onto a signal that travels from this point on the board to that point on the board. This signal you are focusing on is not necessarily a single PCB net though. The signal might be one branch of A0 in a design that you intend to route in a T-branch topology, with the other branch of A0 being another signal you need to focus your attention on as well, and be able to compare the route lengths of these two signals. Or the signal might include a series termination component in its path (which the PCB editor sees as one component and two PCB nets), and if that signal is in a differential pair, its length needs to be compared to the length of the other signal in that pair.
You can manage these requirements using a feature known as xSignals, where an xSignal is essentially a user-defined signal path. You select the source pad and the target pad (in the workspace or in the PCB panel) then right-click on either to define that signal path as an xSignal. As well as interactively defining an xSignal by its start and end pads, you also can run the intelligent xSignals Wizard, whose heuristics will help you to quickly set up a large number of xSignals between the chosen components. These xSignals can then be used to target design rules to your high-speed signals. The software understands the structure of these xSignals; for example, calculating the overall length of multiple nets connected through a termination component, as well as the distance through that termination component.
The PCB panel includes an xSignal mode that is used to examine and manage the xSignals. The panel also provides feedback on the signal length, highlighting xSignals that are close to meeting (yellow) or failing to meet (red) the applicable design constraints. In the image below the xSignal lengths of the CLK1 differential pair are different in length by more than allowed by the applicable Matched Length design rule. The panel includes the Signal Length, which is an accurate point-to-point length. Traditional length inconsistencies, such as tracks within pads and stacked track segments, are resolved, and accurate via span distances are used to calculate the Signal Length.
Main article: Controlled Impedance Routing
Traditionally, board designers would define the widths and thickness of the routing by entering a dimension for the width and selecting a thickness of copper for that layer. This was generally sufficient since you only needed to ensure that the current could be carried and the required voltage clearances were maintained. This approach is not sufficient for the high-speed signals in your design, for these you need to control the impedance of their routes.
Controlled Impedance routing is all about configuring the dimensions of the routes and the properties of the board materials to deliver a specific impedance. This is done by defining a suitable impedance profile, and then assigning that profile to the critical high-speed nets in the routing design rules.
Impedance profiles are defined in the PCB editor's Layer Stack Manager (Design » Layer Stack Manager). The Layer Stack Manager opens in a document editor, in the same way as a schematic sheet, the PCB, and other document types do.
Once the layer properties have been configured, switch to the Layer Stack Manager's Impedance tab to add or edit single or differential impedance profiles.
The routing impedance is determined by the width and height of the route, and the properties of the surrounding dielectric materials. Based on the material properties defined in the Layer Stack Manager, the required routing widths are calculated when each impedance profile is created. Depending on the material properties, the width may change as the routing layer is changed. This requirement to changes widths as you change routing layers is automatically managed by the applicable routing design rule configured in the PCB Rules and Constraints Editor (Design » Rules).
For most board designs, there will be a specific set of nets to be routed with a controlled impedance. A common approach is to create a net class or differential pair class that includes these nets, then create a routing rule that targets this class, as shown in the images below.
Normally you manually define the Min, Max and Preferred Widths, either in the upper constraint settings to apply them to all layers; or individually for each layer in the layer grid. For controlled impedance routing you enable the Use Impedance Profile option instead, then select the required Impedance Profile from the dropdown. When this is done, the Constraints region of the rule will change. The first thing you will notice is that the available layers region of the design rule will no longer show all signal layers in the board, it will now only show the layers enabled in the selected Impedance Profile. The Preferred Width values (and diff pair gap) will update to reflect the widths (and gaps) calculated for each layer. These Preferred values cannot be edited but the Min and Max values can, set these to suitable smaller/larger values.
For single-sided nets, the routing width is defined by the Routing Width design rule.
The routing of differential pairs is controlled by the Differential Pair Routing design rule.
► Learn more about Differential Pair Routing
So how do you know what target impedance to select? This is normally driven by the characteristic source impedance of the logic family or technology being used. For example, ECL logic has a 50Ω characteristic impedance, and TTL has a source impedance range of 70Ω to 100Ω. 50Ω to 60Ω is a common target impedance used in many designs, and for differential pairs, 90Ω or 100 Ω differential impedance is common. Remember, the lower the impedance the greater the current drain, the higher the impedance the more chance there will be EMI emitted, and the more susceptible that signal will be to crosstalk.
A 100Ω differential pair can also be viewed as two, 50Ω single-ended routes that have the same length. This is not exactly correct due to the coupling that occurs between the pair, which becomes stronger as they become closer, reducing the differential impedance of the pair. To maintain 100Ω differential impedance the width of each route can be reduced, which slightly increases the characteristic impedance of each route in the pair by a few ohms.
Main article: Layer Stack Management
The materials used for the layers in your board, their dimensions, and the number of and order that the layers are arranged, are all defined in the Layer Stack Manager. Here you configure the various layers that are needed to fabricate the final board including the copper signal and plane layers, the dielectric layers that separate the copper, the cover layers, and the component overlay.
Main article: Defining the Via Types
As mentioned in the overview section of this article, vias affect the impedance of the signal routing and are a key consideration in high-speed design. As well as the length, hole diameter, and via land area affecting the impedance that the signal sees, any unused portion of a via barrel can act as a stub, contributing to signal reflections. To manage this, various layer-to-layer via styles can be fabricated, including Blind, Buried, µVia, and Skip Vias. These via types are all supported in Altium Designer.
Vias are defined as part of the layer stack, in the Layer Stack Manager's Via Types tab. Back drilling of unused via barrels is also supported, these are defined in the Layer Stack Manager's Back Drills tab (Learn more about configuring the board for back drilling).
Quantitative studies have been performed to understand the impact of vias, such as the Altera Application Note AN529 Via Optimization Techniques for High-Speed Channel Designs.
Summarizing this study and other references, the following guidelines are given to help minimize the impact of vias:
A good quality return path is essential for each high-speed signal in the design. Whenever the return path deviates and does not flow under the signal route, a loop is created and this loop results in EMI being generated, with the amount being directly related to the area of the loop.
A good quality return path is one where:
There is general agreement that a ground plane should not be split unless there is a specific requirement for it and you understand how to define and manage it. Instead, the components should be arranged to keep noisy components separate from quiet components, and to also cluster components by the supply rail that they use.
Other points to keep in mind about power and ground planes include:
To help with the task of visually checking the return paths, you can configure the display so you can more easily examine the return path under the critical route paths.
To do this:
Your net(s) will stand out, and any splits or discontinuities that lie in the return path, such as split lines or blowouts created by through-hole pads and vias, will be easier to see.
Breaks or necks in the return path can be detected by the Return Path design rule. The Return Path design rule checks for a continuous signal return path on the designated reference layer(s) above or below the signal(s) targeted by the rule. The return path can be created from fills, regions, and polygon pours placed on the reference signal layer, or it can be a plane layer.
The return path layers are the reference layers defined in the Impedance Profile selected in the Return Path design rule. These layers are checked to ensure the specified Minimum Gap (width beyond the signal edge) exists along the signal's path. Add a new Return Path design rule in the High Speed rule category.
The image below shows return path errors detected for the signal,
NetX, with a Minimum Gap setting of
0.1mm. It can be easier to locate Return Path errors by configuring the DRC Violation Display Style to show Violation Details but not the Violation Overlay ( show image), in the Preferences dialog. Doing this highlights the exact locations where the rule has failed, rather than the entire object(s) in violation.
The definition of differential pairs can be done during schematic capture, or they can be defined once the design has been transferred to board layout. A core requirement of defining a pair on the schematic is to include an
_N at the end of the Net name for each of the relevant nets. Differential pairs are identified on the schematic by placing a Differential Pair directive on each net, or by placing one on a Blanket directive, where the Blanket directive overlays a set of enclosed differential-style Net Labels, as shown in the image below.
Working with Differential Pairs:
_Npad to commence routing, then use the Spacebar to cycle through the available exit routing shapes. The routing behavior is the same as single net routing, press Shift+F1 for a list of interactive routing shortcuts. As you approach the target pads, press Ctrl+Click to complete the routing up to the pads.
Differential Pair rules of thumb:
A key requirement of managing high-speed signals on a board is to control and tune their route lengths.
The delay caused by the length of the pin within the device package is supported, to learn more read about Pin Package Delay.
Nets that include serial components in their path are managed by defining xSignals.
To understand how the settings of these two rules are resolved when both are present in a design, refer to the Length Tuning page.
Current route lengths are displayed in the Nets mode of the PCB panel, and are updated as you route. The Routed length value will go yellow as you approach the target length, and turn red if you exceed it.
If there is a Length rule and/or a Matched Length rule defined, you can monitor the length during interactive routing or length tuning by displaying the Length Tuning Gauge. While you are routing, use the Shift+G shortcut to toggle the Gauge on and off.
The Gauge shows the current Routed Length as a number over the top of the slider, while the slider shows the Estimated Length. During length tuning the
Estimated Length = Current Routed Length; if you are using the Gauge during interactive routing then the
Estimated Length = Routed Length + distance to target (length of connection line).
MinLimit) is 46.58
MaxLimit) is 47.58 (obscured by the green bar in the image above)
TargetLength) is 47.58 (route length of the longest net in the set, equal to
Route lengths can be tuned after the routing is complete, using the Interactive Length Tuning command, or the Interactive Diff Pair Length Tuning command (Route menu). These commands add accordion sections to the routing, in a choice of three shapes.
If there is an applicable Length rule and Matched Length rule, the length tuning tool considers both of these rules and works out the tightest set of constraints. So if the maximum length specified by the Length rule is shorter than the longest length targeted by the Match Length rule, then the Length rule wins and its length is used during tuning.
To see which rules are being applied or to change the accordion properties during length tuning, press Tab to open the Interactive Length Tuning mode of the Properties panel, as shown below. Note the Target Length, this is the Max Limit of the strictest applicable rule settings.
To tune the length of a net, run the command and then click anywhere along the net's length. Move the cursor so that it follows the path of the route, tuning accordion sections will be added as you do. Tuning sections will continue to be added until the length requirements defined by the applicable design rule(s) have been satisfied. If the cursor moves outside the bounds of the tuning accordions, the accordion shapes will disappear - when the cursor is moved so that it is back within the bounds of the accordion shape, they will re-appear.
► Learn more about Length Tuning
While it is not possible to derive a universal set of rules that apply to every high-speed design, it is possible to follow good design practices that will help you succeed with your high-speed design. There are a number of industry experts that deliver practical and popular training courses on high-speed design. Use the links below to learn more, and to research specialized training options.
The author gratefully acknowledges the work of the following industry experts, this article is an attempt to summarize their collective knowledge.
PCB Layout - Learn EMC website
Keith Armstrong articles, EMC Information Centre (free registration required)
The Electronic Packaging Handbook - Glenn R. Blackwell
The Printed Circuits Handbook - Clyde Coombs and Happy Holden
The HDI Handbook - Happy Holden and others
Via Optimization Techniques for High-Speed Channel Designs - Altera Application Note AN529
High-Speed PCB Design Considerations - Lattice Semiconductor Application Note TN 1033
Measuring a Signal's Flight Time - Chris Grachanen, EDN