Working in harmony with Altium Designer's interactive routing and BGA escape routing capabilities is the pin, differential pair, and part swapping system. This feature provides all the benefits of traditional pin-swapping systems, but takes advantage of Altium Designer's intimate understanding of the net assignments in the design. During a pin swap operation, Altium Designer analyzes the net assigned to the chosen pin, and dynamically reassigns the net on the pin and any connected copper.
This level of functionality means that partially routed nets and pre-routed multilayer escapes from complex BGA devices can be swapped. Differential pairs can also be swapped, taking advantage of the knowledge about differential pin-pairs on FPGAs.
At the PCB level, the system includes a powerful automatic optimizer that uses this information to dynamically re-assign nets to improve routability. For example, the system can perform a reconnect on multiple devices that have been escape routed on multiple layers. It will assign these based on matching escape route layers, shortest Manhattan routing distance, and minimum number of crossovers on each layer.
The addition of partial routed net swapping, along with the automatic optimizer, gives you the ability to adopt a hierarchical and iterative routing strategy, escape routing devices first, then routing to the edge of a given area, resulting in finally connecting these sections together. At any time, the automatic swapper can be re-run to re-optimize, based on the updated information provided by the partially routed nets.
There are three categories of swapping:
For each category of swapping, swap groups dictate what can be and what can not be swapped within a component. In the case of pin swapping, pins within a component that share a common pin group are able to be swapped with one another. Similarly for pair swapping and part swapping, it is the pair group and part group values that determine that a differential pair or sub part can be swapped respectively. The swap groups for a component are configured in the Configure Pin Swapping dialog, shown in the image below. It is accessible in the following ways:
A component pin is swappable with another pin in that component when it belongs to the same pin group (has the same pin group value). The pin group is an attribute of each pin in the component and its value can be any alphanumeric string. The pin groups for the entire component are set up in the Configure Pin Swapping dialog.
Consider the schematic shown in the image above, which contains the two 5-Input NOR Gates for the SNJ54S260 component. Each of the nets, INA0 to INA4, can be swapped with each other due to the nature of the NOR Gate. Similarly, each of the nets INB0 to INB4 can be swapped, however a INAx net can not be swapped with a INBx net.
The swapping constraints for the NOR gate are defined in the Configure Pin Swapping dialog. Giving the nets INAx the swap group 1, and the nets INBx the swap group 2 ensures that swapping will only be performed by the system in such a way that it is consistent with the component logic. Leaving the Pin Group value for a pin empty denotes that the pin is unavailable for swapping.
It is common for a component to consist of multiple functionally equivalent subparts. Part swapping allows the nets of such equivalent sub-parts to be swapped. Consider again the component shown in the image above. Both NOR gates offer identical functionality and the nets (INA0, INA1, INA2, INA3, INA4, OUTA) are able to be swapped with nets (INB0, INB1, INB2, INB3, INB4, OUTB).
Part swapping for a component is configured with the part group and sequence ID attributes. These are both text attributes and are accessible in the Part Swapping tab of the Configure Pin Swapping dialog, as shown below. The image below also displays the part group and sequence ID settings corresponding to the component shown in the image above. The part group indicates which sub-parts are able to be swapped with one another. The two sub-parts are able to be swapped and consequently, in the image below, their part groups are given the same value of 1.
The sequence ID attribute determines equivalence of the pins between swappable sub-parts. In the NOR gate example it is important that the input pins are not interchanged with the output pins when a part swap occurs. The image below shows the sequence ID are set so that OUTA swaps with OUTB, INA0 swaps with INB0, INA1 swaps with INB1 and so on.
Note that Part Swapping is only available for components designed as sub-parts as it is based upon swapping all the nets between two sub-parts.
The swapping of differential pairs is governed by the value of the pair group for a differential pair. The pair group attribute is accessed in the Differential Pair Swapping tab of the Configure Pin Swapping dialog. There are three modes in the Differential Pair Swapping tab that can be set by accessing the drop down box in the lower left corner.
In the PCB editor pin, pair, and part swaps are performed by exchanging nets on component pads and corresponding copper. When the changes are merged into the schematics there are two ways that a pin swap can be handled, either by swapping the pins on the component symbol, or by swapping net labels on the wires attached to the pins. Each approach has its advantages and disadvantages.
Swapping the pins will always work on the schematic, but it may mean that this instance of the component symbol is no longer the same as it was defined in the library. In this situation it means the symbol cannot be updated from the library, and it also means that other instances of the same component in this design will have a different pin arrangement. Thus, this approach is ideal for simple components, such as a resistor arrays.
Performing the swap on the schematic by swapping net labels can only be done if the connectivity is established through the net labels, and if the pins are not hard-wired together. The advantage of this approach is that the component symbol does not change, and can be updated from the library at a later date. This approach is the best choice for a complex component, such as a FPGA, where physically moving two pins on the symbol could result in an I/O bank-based symbol presenting incorrectly.
You may determine how the swaps are performed by choosing the Adding / Removing Net-Labels or Changing Schematic Pins options in the Allow Pin Swapping Using these Methods section of the Project Options - Options dialog, as shown below.
The swap group attributes needed to setup pin, pair, and part swapping within a component are stored in the Schematic components. However, it is in the PCB editor where this information is used. Each PCB component has an option to allow pin swapping.
The swapping options for a PCB component can be configured in the Properties panel, which presents the properties for that component when it is selected in the design space. The options can be found in the Swapping Options region of the General tab.
The Configure Swapping Information in Components dialog lists all components used in the design (including SCHlib/PCBlib) with their current swap settings. When accessed from the PCB editor, the Configure Swapping Information in Components dialog includes an additional column for enabling/disabling swapping of each component on the board, called Enable in PCB. The Configure Swapping Information in Components dialog is accessed from the Tools » Configure Pin Swapping command.
The Configure Swapping Information in Components dialog includes a powerful right-click menu, making it easy to quickly copy the settings from one component to another, or enable/disable multiple components with a single click.
Double clicking on a component in the Configure Swapping Information in Components dialog will open the Configure Pin Swapping dialog for that component, where you can define the swap group settings for pins, differential pairs, and subparts.
Interactive swapping allow pins, differential pairs, or subparts to be swapped one at a time in the PCB editor. The interactive swapping commands are found in the Tools » Pin/Part Swapping sub-menu. Once the command is selected from the menu, the pins that are available for swapping are highlighted. The steps required to perform a swap are displayed on the status line:
The stages of interactively part swapping the Dual 5-input NOR gate component are shown in the two images below. There are two subparts that can be swapped, meaning each of their five pins can be selected, as shown in the image above. Pin 8 is selected corresponding to the subpart U2B. The system then highlights the pins of subpart U2A that can be swapped.
The Automatic Pin/Net Optimizer is a two-stage tool. Select Tools » Pin/Part Swapping » Automatic Pin/Net Optimizer from the PCB editor menu to perform an automatic optimization.
The Automatic Pin/Net Optimizer first runs a fast single-pass optimizer that attempts to minimize cross overs and connection lengths, but may actually increase them. When this is complete you will be asked if you want to run the iterative optimizer. The iterative optimizer will perform multiple passes in an attempt to reduce the number of cross overs and connection lengths.
When you configure the swap groups in the Configure Pin Swapping dialog the edits you make are immediately applied to the schematic components, regardless of which editor was active when the command was launched. However, design changes that are a result of you performing a pin, differential pair, or subpart swap in the PCB editor are propagated back to the schematic using the standard Design Update process.
Pin, pair, and part swaps are passed back to the schematic in the same way that other design changes are transferred - by selecting Design » Update from the menus. Depending on how the Allow Pin-Swapping options are configured in the Project Options - Options dialog, pin swaps will be performed as:
If the schematic does not update to show swapped pins or parts, press the End key to refresh the display.
Other than the obvious advantages that intelligent pin, pair, and part swapping provides, the ability to swap partially routed sub-nets brings a new dimension to swapping that is ideal for working with large capacity FPGAs. The dynamic net re-assignment allows you to use a multi-stage design process with progressively refined pin/net assignments
In this stage, the FPGAs' and other device pins have their net assignments setup in whichever way is easiest at the schematic level. Usually, this means merely adding net labels in numeric bus order to the pins on the FPGA. The Smart Paste feature in the Schematic Editor is ideal for doing this.
The design can be transferred to PCB layout, where there will be a lot of connection crossovers because of the random assignment at the schematic level. Running the Automatic Net/Pin Optimizer command will quickly provide a large reduction in the number of crossovers. The result does not need to be ideal yet, as it is used to primarily make connections more visually manageable at the PCB level.
Fanout and Escape routing can now be performed on large devices on the PCB (right-click on the component to selectively perform fanout/escape routing). This may worsen the previously optimized assignments, but that does not matter at this point.
Run the automatic optimizer again. This time, it will take advantage of the pre-routed sections of fanout/escape routing.
You can now treat the ends of the escape routes as 'targets' to route towards. Ignoring the actual connection lines, due to the fact that you can route from the other ends of the nets toward the nearest escaped I/O route (spatially and by layer) on the PCB, rather than the one that is on the same net. The connections will not line up. Instead, you will end up with a series of small gaps between the escape routing from the FPGA I/O pins, as well as your routing coming from other parts of the PCB. The image below shows a simple example of this.
Run the automatic optimizer again and it will assign the routed subnets to the closest possible escaped I/O pin. This will leave you with a set of very short connections to complete. The automatic optimizer has special routines to produce a good result in this case. These can now be interactively or automatically routed.
Use the interactive swapper to perform any specific pin swap changes that you need.
When you are ready to propagate these pin assignments back to the schematic, it is a good idea to disable pin changes on the schematic symbols. This is because FPGAs are often presented as multi-part components, with each bank of pins being a separate schematic part. Moving pins from one part to another would result in these symbols becoming logically incorrect, as the bank symbol would include pins that did not belong in that bank. In this situation, performing pin swaps by changing net labels is the correct approach.
This process can be run as many times as required, and at any time during the design process.