Violations Associated with Nets when Validating a Design in Altium Designer

This document is no longer available beyond version 21. Information can now be found here: Violations Associated with Nets for version 24

Applies to Altium Designer version: 21

The Violations Associated with Nets region on the Error Reporting tab of the Project Options dialog
The Violations Associated with Nets region on the Error Reporting tab of the Project Options dialog

Logical, electrical, and drafting awareness in your schematic diagram can be verified during design project verification according to rules defined as part of the options for the design project – on the Error Reporting and Connection Matrix tabs of the Project Options dialog.

For a detailed overview of verifying your captured design, see Verifying Your Design Project.

The Violations Associated with Nets region on the Error Reporting tab of the Project Options dialog allows specifying the severity level associated with check of net-related violations that can exist in source documents when validating a project. Use the following collapsible sections to access information on each violation available in this region.

可用的功能取决于您的 Altium Designer 软件订阅级别