This tab of the Project Options dialog enables you to define the reporting levels for each of the possible electrical and drafting violations that can exist on source schematic documents when compiling the project. When the project is compiled, these violation settings will be used in conjunction with the settings on the Connection Matrix tab to test the source documents for violations.
Any violations that are found that have a report level of Warning, Error or Fatal Error will be displayed as violation messages in the Messages panel. In addition, if compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it.
This is one of multiple tabs available when configuring the options for a project accessed from within the Project Options dialog. To access this dialog:
This list presents all possible electrical and drafting violations that can exist on the source documents of the project. Violations themselves are gathered into the following categories:
Each specific violation type is presented with the following fields:
The following commands are available from the right-click menu:
One option of interest is Nets with only one pin. This can be used to detect single node nets where a pin has been connected to a Port for example, but does not connect to another pin. This is set to Error by default and can be changed to No Report if the single node net is intentional.