Altium NEXUS Documentation

印刷电子_AD

Created: December 26, 2018 | Updated: December 26, 2018

印刷电子设计

电子产品设计和开发的一个令人兴奋的发展是能够将电子电路直接印刷到基板(例如塑料模制件)上,使之成为产品的一部分。

这种面向表面的实现技术被称为结构电子设计或印刷电子。虽然“印刷电子”这一术语并不是对该技术的精确描述,但由于印刷不是用于创建该技术的唯一技术,因此该术语具有广泛的行业认可度,并将在本页中使用。

目前正在开发多种印刷电子制造技术,包括:使用导电油墨进行3D打印;可以制造导体以及简单电路元件(例如晶体管)的冲压技术;以及激光沉积技术,此技术可以极小的尺度上建立传导路径,而且具有超高精度。

印刷电子将成为一项关键技术,让电子产品融入新市场。印刷电子可以在电路和产品之间建立紧密连接。从直接连接到身体的柔性传感器到多传感器和允许机器人手持软塑料杯承接液体的指尖形模制,印刷电子将使创新解决方案在许多细分市场中得以发展。

技术

就技术提供的内容而言,任务是一样的 - 将电子元件通过导电通路连接在一起,形成一个执行特定功能的电子电路。不同之处在于电路构建的方法。

The layer-oriented fabrication technology used to make a traditional PCB is a reductive process. Each conductive layer starts as a continuous sheet of conductive material, such as copper, which is then etched away, leaving only the copper that forms the required conductive pathways. It is also a multi-staged process, as the individual conductive layers are sandwiched together with alternating layers of insulation, and various drilling and post-plating processes applied.

Printed electronics is an additive process, the signal pathways are printed directly onto a substrate. If a subsequent signal pathway needs to cross an existing pathway, a small patch of insulation is printed directly in the required location. Acting like a tiny bridge, it allows the new signal pathway to be printed across the existing pathway, without connecting to it. As an example, if the design is using the DuPont InMold technology, the circuit is first printed onto a flat plastic substrate, which is then thermoformed and injection molded into the final product shape. 

Using printed electronics, the humble rigid fiberglass printed circuit board substrate is no longer required. Instead the circuit is formed directly as a part of the product, the conductors ultimately following the shape and contours of the product's surface. As there is less material used and less waste, printed electronics will ultimately become a more cost effective approach than a traditional PCB, in many situations. 

NOTE - at this stage only flat substrate surfaces are supported.

Altium's developers will continue to work closely with companies that develop products using printed electronics, enhancing the feature set over future releases of the software.

在Altium软件中进行印刷电子设计

除了印刷设计的基板之外,印刷电子产品中没有物理层 - 导电通路直接印刷在基板上。如果设计需要相互交叉的路径,则在该位置印刷一小片介电材料,然后充分扩展到需要交叉的范围以外,实现所需的绝缘隔离水平。

驱动打印过程所需的输出是使用标准输出格式生成的,例如Gerber。

输出将包含一个记录以下内容的文件:

  • 每个导电印刷通道 - 基本上与传统PCB中的铜布线层相同
  • 每个介质印刷通道 - 由于印刷了介质片,输出文件中也指定了它们的形状,例如Gerber文件

定义层堆栈

So how are these multiple printing passes defined in the PCB editor? In printed electronics, each printing pass requires an output file, so rather than thinking of it as a series of copper layers separated by dielectric layers, think of it as a set of printing passes, with each pass either being a conductive layer of ink, or a non-conductive layer of ink.

To create a printed electronics design, first create a new PCB (File » New » PCB).

A new PCB defaults to 2 copper layers, separated by a dielectric layer, as shown in the Layer Stack Manager.A new PCB defaults to 2 copper layers, separated by a dielectric layer, as shown in the Layer Stack Manager.

A new board is configured as a printed electronics design in the Layer Stack Manager using the button, or by selecting the Tools » Features » Printed Electronics command.

When the Printed Electronics feature is enabled, the dielectric layer is removed.When the Printed Electronics feature is enabled, the dielectric layer is removed.

When this is done the dielectric layer between the 2 copper layers disappears. Why? because printed electronics requires an output file for every layer, so dielectric layers are not used as they are not used to generate output files. Instead, non-conductive layers are added. Dielectric shapes, referred to as patches, can be manually or automatically defined on these layers where ever signal paths need to cross each other on the conductive layers.

Non-Conductive layers can be inserted between the Conductive layers, and dielectric patches defined on them.Non-Conductive layers can be inserted between the Conductive layers, and dielectric patches defined on them.
Right-click on a layer to: insert a layer above or below; move a layer up or down; delete a layer. Printed electronics do not use the Bottom Solder or Bottom overlay, these have been removed.

Once the layers have been added, set the properties of the material for each layer.

Use the elipsis button to select the material to use for each printed layer.Use the elipsis button to select the material to use for each printed layer.

Material Selection

The material used in both traditional PCB design and printed electronic design are selected in the Layer Stack Manager's Material Library.

When the Layer Stack Manager is open, use the Tools » Material Library command to open the Altium Material Library dialog.

  • The Material Library includes materials for both conductive and non-conductive layers.
  • New materials can be defined in the library, click the New button at the bottom of the dialog. If user-defined materials are created, they can be saved to and loaded from a user-defined materials library.
  • To select a material for a specific layer, click the ellipsis control () in the Material cell for that layer in the Layer Stack Manager. The Select Material dialog will open, displaying only the materials that are suitable for that layer Type. Select the required material and click OK.

Routing the Nets

  • The nets in a printed electronics design are routed in the same way as a traditional PCB, using the Interactive Routing command.
  • Conductive layer transitions are performed using the + and - keys on the numeric keypad, or the Ctrl+Shift+Wheelroll shortcut.
  • When you change layers during routing a via is added, the via properties are determined by the applicable Routing Via Style design rule.

Why are vias needed?

The software needs to place a via to maintain the connectivity of the net during routing, and also to manage the connectivity when the routing is modified by pushing or dragging. Vias are also needed for net analysis during design rule checking.

The vias can have their diameter set to the same size as the routing width.

Increasing the Route Thickness

The route thickness can be built up if required, for example to implement a structure such as a printed antenna. This is achieved by placing multiple routes on top of one another, on different conductive layers.

Adding Dielectric Shapes

Once the nets have been routed, the next step is to create the dielectric patches needed to separate any different-net cross overs.

  • Dielectric shapes are defined on non-conductive layers. They can be defined manually, or automatically created using the Dielectric Shapes Generator.
  • Manual shapes can be created from Arcs, Lines, Fills or Solid Regions. Solid Region objects offer the greatest flexibility, as their edges can be adjusted to create virtually any shape.
  • The software also includes an automatic dielectric shape generator. The concept here is to first complete the routing as required on conductive layers, placing vias to switch between layers (requirements?).
  • When the routing is complete, run the Tools » Printed Electronics » Generate Dielectric Patterns command to open the Dielectric Shapes Generator dialog.
  •  The Dielectric Shapes Generator will identify all cross overs and add dielectric patches, in accordance with the settings in the Layers region of the dialog. If no dielectric layer is selected in the Select Dielectric Layer dropdown, dielectric shapes will be created for all cross overs between all layers, on appropriate dielectric layers.
  • In Auto mode, the dielectric shape is automatically expanded to satisfy the requirement of the applicable Clearance Constraint design rule.
  • Use the Fill Gaps option to merge adjacent dielectric patches into larger patches.
  • In Manual mode the generator builds a shape to match the shape formed by the crossed-over objects, then expands that shape out by the distance entered. Clearance constraint design rules are not considered in this mode, for example if two conductive pathways are within the distance allowed by the clearance constraint but do not cross over, no dielectric shape will be created in that location.

The Dielectric Shape Generator requires the Patterns Generator extension to be installed. Check the Dielectric Shapes Generator dialog page for more information.

When the Generator is run it will remove all shapes on the target layer(s), then recreate them. If shapes have been defined manually, lock them before running the Shape Generator.

Net Connectivity and Design Rule Checks

Online DRC is not supported when the layerstack is configured as Printed Electronics because of the different logic used to define violation conditions; such as nets crossing on different layers being flagged as a short circuit. Once the routing is complete and the isolation patches have been defined, click the Run Design Rule Check button in the Design Rule Checker dialog (Tools » Design Rule Check) to perform a batch DRC.

Notes about net connectivity and Design Rule Checks:

  • When a net needs to switch to another conductive layer, insert a via.
  • Touching / crossing tracks that are on different layers, are considered connected. If they are in the same net this is flagged as a broken net, if they are in different nets this is flagged as a short circuit.
  • A dielectric shape is required to isolate touching / crossing tracks, this shape is placed on a non-conductive layer. The dielectric shape can be placed manually, or by the Dielectric Shape Generator. The dielectric shape must extend beyond the edges of the crossing tracks sufficiently to satisfy the applicable clearance constraint design rule.
  • For a printed electronic design, design rule checks for short-circuits, clearance violations and unrouted nets behave as described below.

Short Circuit Design Rule

In a Printed Electronics design, when different nets cross over on different layers, they are flagged as a short circuit. These cross-overs are isolated by placing a dielectric patch on a non-conductive layer.

Clearance Design Rule

Net to net clearances are tested on all layers, not just the same layer.

Unrouted Net

Layer transitions require a via for the net analyzer to recognize that the net is not broken.

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