就技术提供的内容而言，任务是一样的 - 将电子元件通过导电通路连接在一起，形成一个执行特定功能的电子电路。不同之处在于电路构建的方法。
The layer-oriented fabrication technology used to make a traditional PCB is a reductive process. Each conductive layer starts as a continuous sheet of conductive material, such as copper, which is then etched away, leaving only the copper that forms the required conductive pathways. It is also a multi-staged process, as the individual conductive layers are sandwiched together with alternating layers of insulation, and various drilling and post-plating processes applied.
Printed electronics is an additive process, the signal pathways are printed directly onto a substrate. If a subsequent signal pathway needs to cross an existing pathway, a small patch of insulation is printed directly in the required location. Acting like a tiny bridge, it allows the new signal pathway to be printed across the existing pathway, without connecting to it. As an example, if the design is using the DuPont InMold technology, the circuit is first printed onto a flat plastic substrate, which is then thermoformed and injection molded into the final product shape.
Using printed electronics, the humble rigid fiberglass printed circuit board substrate is no longer required. Instead the circuit is formed directly as a part of the product, the conductors ultimately following the shape and contours of the product's surface. As there is less material used and less waste, printed electronics will ultimately become a more cost effective approach than a traditional PCB, in many situations.
除了印刷设计的基板之外，印刷电子产品中没有物理层 - 导电通路直接印刷在基板上。如果设计需要相互交叉的路径，则在该位置印刷一小片介电材料，然后充分扩展到需要交叉的范围以外，实现所需的绝缘隔离水平。
So how are these multiple printing passes defined in the PCB editor? In printed electronics, each printing pass requires an output file, so rather than thinking of it as a series of copper layers separated by dielectric layers, think of it as a set of printing passes, with each pass either being a conductive layer of ink, or a non-conductive layer of ink.
To create a printed electronics design, first create a new PCB (File » New » PCB).
A new board is configured as a printed electronics design in the Layer Stack Manager using the button, or by selecting the Tools » Features » Printed Electronics command.
When this is done the dielectric layer between the 2 copper layers disappears. Why? because printed electronics requires an output file for every layer, so dielectric layers are not used as they are not used to generate output files. Instead, non-conductive layers are added. Dielectric shapes, referred to as patches, can be manually or automatically defined on these layers where ever signal paths need to cross each other on the conductive layers.
Right-click on a layer to: insert a layer above or below; move a layer up or down; delete a layer. Printed electronics do not use the Bottom Solder or Bottom overlay, these have been removed.
Once the layers have been added, set the properties of the material for each layer.
The material used in both traditional PCB design and printed electronic design are selected in the Layer Stack Manager's Material Library.
When the Layer Stack Manager is open, use the Tools » Material Library command to open the Altium Material Library dialog.
The software needs to place a via to maintain the connectivity of the net during routing, and also to manage the connectivity when the routing is modified by pushing or dragging. Vias are also needed for net analysis during design rule checking.
The route thickness can be built up if required, for example to implement a structure such as a printed antenna. This is achieved by placing multiple routes on top of one another, on different conductive layers.
Once the nets have been routed, the next step is to create the dielectric patches needed to separate any different-net cross overs.
Online DRC is not supported when the layerstack is configured as Printed Electronics because of the different logic used to define violation conditions; such as nets crossing on different layers being flagged as a short circuit. Once the routing is complete and the isolation patches have been defined, click the Run Design Rule Check button in the Design Rule Checker dialog (Tools » Design Rule Check) to perform a batch DRC.
Notes about net connectivity and Design Rule Checks:
In a Printed Electronics design, when different nets cross over on different layers, they are flagged as a short circuit. These cross-overs are isolated by placing a dielectric patch on a non-conductive layer.
Net to net clearances are tested on all layers, not just the same layer.
Layer transitions require a via for the net analyzer to recognize that the net is not broken.