IV

Strategizing Your PCB Layout

With your material selections finalized, it is now time to dive into the specific details of your PCB layout. While individual engineering workflows might differ from one designer to the next, there are a number of primary design considerations that have a need for precise DFM requirements to consider a board 100% ready for manufacturing. In the following sections you will learn the specifics of strategizing your PCB layout including SMT and through-hole specifications, silkscreen documentation, solder mask applications, and more.

Deciding Between Through-Hole or SMT

Choosing plated through-hole (PTH) components or surface mount (SMT) will have a direct impact on your overall costs and manufacturing time. It is recommended to stick with SMT for professional board designs as this results in quicker board turnarounds and higher reliability

Silkscreen and Component IDs

All component outlines on your silkscreen should be marked with a reference designator and polarity indicators (if applicable).

Component Reference Designators Refer to IPC-2612 for a list of industry-standards

Solder Mask

The solder mask is a thin, lacquer-like layer applied as a final coating to your PCB to protect various features including copper traces and Copper Pour that should not be soldered.

Vias and Holes

Vias are a critical part of every PCB design and are responsible for transmitting electrical current between layers.

Via Clearance Requirements

Standard vias should maintain minimum clearances from adjacent conductors, and the clearance will largely depend on whether the via is tented or exposed.

Via Size Guidelines

When designing plated via holes, it is recommended to maintain a 8:1 aspect ratio between the hole diameter and t he substrate thickness. Figure 5 depicts typical standard drill sizes:

Figure 5: Standard Drill Sizes for Vias and Holes
Annular Rings

The annular ring is the difference between the pad diameter and the corresponding drill diameter. Figure 6 shows how to easily calculate the width of an annular ring:

Annular Ring Width =
(Diameter of the pad –
Diameter of the hole) / 2
 
Figure 6: Recommended Annular Ring Width
Exposed Vias

Exposed vias are exposed electrical connections that are not covered with solder mask.

Tented Vias

Tenting a via covers the via hole and annular ring with soldermask, and should be set as the default method in your design workflow.

Via-in-Pads and Micro Vias

Via-in-pads allows for close placement of bypass capacitors and makes routing easier for any ball pitch BGAs, as well as assists with thermal management and grounding.

Blind and Buried Vias

Similar to through-holes, blind and/or buried vias (BBV) are holes that connect one or more layers. In this process, a blind via connects an outer layer to one or more inner layers but not to both outer layers, and a buried via connects one or more inner layers, but not to an outer layer. See Figure 7 for an example of a blind and buried via application:

Figure 7: Blind and Buried Vias
Aspect Ratio Plating

Aspect ratio is the ratio between the thickness of the board and the size of the drilled hole (before plating). Figure 8 shows a visual example of how aspect ratios are determined on a PCB:

Figure 8: Determining an Aspect Ratio for a PCB

Trace Routing to Component Lands

When you have a component’s termination that could generate heat and is connected to a large trace, the heat transfer produced can lead to a poor solder joint. In the following sections you will learn how to mitigate these issues.

Necking a Trace

A general guideline for necking a trace is to keep it no wider than 0.010” where it connects to the pad and run it at least 0.010” before it connects to the large trace. Figure 9 shows an example of this process:

Figure 9: Connecting Large Traces to Component Lands (Good Design)
Connecting Pads to Traces

Every pad should be connected to its own trace, and it is recommended to have the routing from either outside the edges or inside the edges of the pads while keeping the routing symmetrical.