Contact our corporate or local offices directly.
Parent page: More about Schematics
What does it mean to compile the design? And why does the design need to be compiled; why can't the software just keep track of the connectivity as you create it on my schematic?
Ultimately, the software needs to build a connective model of the entire design for both the schematic and the PCB. To do this with persistence - where the software is keeping track of the connectivity at all times - the component and connective data for the entire design would need to be available when the design is opened, which would require all the data to be stored in a single file. Storing all of the data, for all of the sheets in your large multi-sheet schematic, in a single file is possible, but, for a number of reasons, is not the best approach.
To draw an analogy to software development, it would be like storing all of the source code for your entire application in a single file, and coding in a development environment that recompiles every time you you make a change. Neither of these are something that any coder would want. Software development tools allow the source to be spread across multiple files, and they separate the creation process from the analysis and compilation process. Doing this allows the developer to freely create, edit and modify their source code, using a file structure they choose. They compile the source to generate the working code only when they think it is ready for compilation.
Using this same approach, the schematic designer can freely place, wire, re-arrange, re-name, and add and delete content from their schematic design. When the designer thinks it is ready, they compile it - verifying it and building the internal connective model. This approach also supports a one-file-per-schematic-sheet model. Using a separate file for each schematic means you can easily bring in content from a previous project, and it also means that multiple designers can work on the same project, at the same time.
When you are ready to compile the design, choose the Compile PCB Project command from the Project menu.
Using this approach, the schematic editor is actually an intelligent drafting tool, rather than a wiring tool. When you connect two pins with a wire you are drafting your design intentions, not creating an actual net. That net is not created until you compile the project, and that process is managed by code outside of the schematic editor. As mentioned, there are a number of advantages to this approach, with the biggest being that the compiled model of the design sits outside of the individual schematic and PCB editors. This compiled model is referred to as the Unified Data Model (UDM). The UDM includes detailed descriptions of every component in the design and how they connect to each other.
A fundamental element of the software is the Unified Data Model (UDM). When the project is compiled, a single, cohesive model is created that sits central to the design process. Data within the model can then be accessed and manipulated by the various editors and services within the software. Rather than using a separate data store for each of the various design domains, the UDM is structured to accommodate all information from all aspects of the design, including the components and their connectivity.
So how do you interact with the unified data model, for example, to trace a net through the design? You do that through the Navigator panel.
Reference article: Navigator panel
If the design is large and spread over many sheets, it can become difficult to follow a net and verify the connectivity in the design by simply looking at the schematics. To help with this process, the Navigator panel is used. The panel gives a view of the entire, compiled design so it will be blank until the project is compiled (Project » Compile PCB Project). The Navigator panel can be opened by clicking the Panels button on the bottom right of the design window then selecting Navigator.
To use the panel:
Main article: More about Components and Libraries
A key aspect of verifying the design is to be confident that the components are correct. Typically this is done as the components are added to your company libraries. Common component errors that will cause board design errors include:
Other component errors that cause design delays and frustrations include:
Main article: Project Options dialog
There are a large number of drafting and electrical checks that can be performed on the compiled design. These are configured as part of the project options. Click Projects » Project Options to open the Project Options dialog (shortcut: C, O). The default settings will not suit every design and, therefore, it is important to become familiar with the options and how to configure them to suit your design.
When you compile, common drafting and editing errors are checked in accordance with the settings in the Error Reporting tab of the Project Options dialog.
The error checks are organized in groups, for example Violations Associated with Nets, Violations Associated with Code Symbols, Violations Associated with Components, etc. The groups are listed alphabetically in the dialog.
The Report Mode of each violation can be changed to one of four values by clicking on it and selecting the desired value in the drop-down:
Generally it is better to first compile the design and examine the warnings with the default settings. For those warnings that are not an issue for the current design, the reporting level can be changed.
One option of interest is Nets with only one pin. This can be used to detect single node nets where a pin has been connected to a Port or Net Label, but does not connect to another pin. This is set to No Report by default and can be changed to Warning to help detect broken nets.
The electrical connectivity is checked in accordance with the settings in the Connection Matrix tab of the Project Options dialog.
The matrix provides a mechanism to establish connectivity rules between component pins and net identifiers, such as Ports and Sheet Entries. It defines the logical or electrical conditions that are to be reported as warnings or errors. For example, an output pin connected to another output pin would normally be regarded as an error condition, but two connected passive pins would not.
Click on the small square in the matrix to change a particular rule. Each rule determines the reporting level for a given pin/net identifier combination. There are four possible values for each rule:
Main article: Messages panel
When the project is compiled, every condition that generate a warning or error is listed in the Messages panel. Note that the Messages panel will only open automatically if there is an error condition. To check for warnings, you will need to open it. Click the Panels button on the bottom right of the application to display the Messages panel. Once the project has been compiled, the panel will list any warnings and errors that have been detected.
It is important to address each warning or error that is detected. The default error settings tend to be conservative since it is better for the software to err on the side of being cautious and let you decide if the testing boundaries can be relaxed. For example, your design may require IO pins to be connected to Input ports, requiring you to adjust the appropriate cell in the Connection Matrix tab. Another common error check to be changed is the Net has no driving source, requiring you to disable that check in the Error Reporting tab.
There will be situations when you want to test the entire design for a certain condition, but you want to ignore a warning/error at a specific point in the circuit. For example, you might want to allow a net to be renamed at a specific location, but only in that location. This can be done by placing a No ERC directive at that location.
Main article: No ERC object
When you need to allow a specific point in the circuit to not report an error, place a No ERC (Electrical Rules Check) directive on that point (Place » Directives » Generic No ERC) meaning "do not flag a warning/error at this location". Set the No ERC symbol style and color to suit its role in the circuit in the No ERC mode of the Properties panel.
Note that No ERC directives can be excluded from printouts, if required, by enabling the relevant option(s) in the Schematic Print Properties dialog.
You can place a Specific No ERC directive directly at the error location from the Messages panel (right-click then choose Place Specific No ERC for this violation as shown in the images below) or at the violation .
Main article: Project Compiler Violations Reference
The software can test for a large number of potential error conditions. There is information available about each error check in the Project Compiler Violations Reference.
Can't perform revision state validation. It occurs when there is a component that has been placed from a server and that server does not support revision state validation.
Contact our corporate or local offices directly.
Complete this form to request a free 15 day trial of Altium Designer: