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With ever-increasing device switching speeds comes the challenge of maintaining the integrity of the signal, and meeting the signal's timing requirements. The signal integrity can be managed through controlled impedance routing, which is achieved through the careful design of both the PCB stackup and the routing widths to be used on each layer.
The timing requirements are met by matching the routed lengths of the signal paths. For a set of 2-pin signal paths, each running from an output pin to a single input pin, calculating and comparing the lengths is a straightforward process. This is not the case for many typical design solutions though where there may be a series termination component in the signal path, or there are more than two pins in the signal, which could then be routed using a Balanced T or a Fly-By routing topology, as shown in the image below.
The designer's job is to translate their design requirements, such as the maximum route length allowed to meet the timing budget, into a set of design rules, such as a Length rule to ensure that the timing is met, and a Matched Length rule to detect potential timing mismatches.
Now the designer sees the signals in terms of their function (eg, 'This address signal must be routed from this connector to each memory device. To achieve that I'll route using a fly-by topology with a termination resistor at the end. I might also require a series terminator at the source'). Even though address A0 passes through a termination resistor, to the designer, that signal is still A0 on the other side of that resistor.
But the PCB editor sees each signal simply as a set of connected pins (commonly referred to as a net) — Net A0 goes from this connector pin to this memory component pin, then to this memory component pin, and so on. As soon as a series termination resistor is added, that address line becomes two discrete nets. This makes it difficult for the designer to specify key design requirements, such as Length and Matched Length design rules.
This can be managed by a feature called xSignals. This feature enables the correct treatment of a high-speed signal path as just that - a path for a signal to travel between a source and destination, through termination components as well as branches.
An xSignal is a designer-defined signal path between two nodes; they can be two nodes within the same net or they can be two nodes in different nets.
xSignals are defined using the following methods:
Alternatively, the following methods are used by selecting objects of interest first, then choosing the appropriate command:
If you have a large number of xSignals to define, it is more efficient to use the Create xSignals Between Components dialog. Accessed via the Design » xSignals » Create xSignals command, the dialog presents Source Components and their Source Component Nets and Destination Components and allows you to create one or many xSignals in a single operation. The approach is to:
The dialog will close and you will be returned to the design space. The new xSignals will be listed in the xSignals mode of the PCB panel.
If you are creating xSignals that include series termination components, a good approach is to use the Create xSignals from connected nets command. The command is available whenever a component is selected either via Design » xSignals sub-menu from the main menus or the right-click xSignals sub-menu.
This command is designed to build xSignals outward from a selected series termination component, such as a resistor or capacitor. It supports both one or more discrete components, and one or more multi-instance pack-style components, such as resistor networks. After running this command, the Create xSignals From Connected Nets dialog will open.
When you define an xSignal, it is between two nodes or pads. However, when you select that xSignal in the xSignals mode of the PCB panel, it will actually follow the path of the connection lines that runs between those two pads, indicating that this is the path that the software assumes the xSignal will be routed. The reason it does this is because it is obeying the topology defined for that net. Net topology is defined by the applicable Routing Topology design rule; the default topology is Shortest.
The simple animation shows a CPU connected to four DDR3 memory chips, which is going to be routed using a fly-by routing strategy. The DRAM_A2 xSignal class contains four xSignals. First, the class is selected, then each xSignal is selected in turn. You can see how the xSignal path follows the topology of the net, which is currently set to the default - Shortest.
Apart from the Design » xSignals » Create xSignals command, there are other xSignal creation commands in the xSignals sub-menu when certain conditions are met.
Below is a summary of the commands and when they are available:
|Create xSignal from selected pins||Immediately creates a single xSignal. This command is available when there are two or more pads selected in the design space, and is the same command presented when you right-click on one of the selected pads.|
|Create xSignals between components||This command is available when components are selected in the design space. When it is run the Create xSignals Between Components dialog opens with the component(s) pre-selected. Ensure that the correct Source and Designation components are selected, then complete the Analysis/Creation process.|
|Create xSignals from connected nets||Use this command when there are one or more series termination components to create xSignals for. Select the termination component(s), then run the command to open the Create xSignals from Connected Nets dialog, ready to complete the process of creating a set of xSignals.|
|Create xSignals||Opens the Create xSignals Between Components dialog. This command is always available.|
One of the challenges of a Balanced T routing strategy is how to equalize the length of the trunks and the branches beyond the T points. The available nodes in the net are only at the pads, so it is not possible to define separate xSignals for the trunk, and from the branch point to the end of each branch. The branch points are indicated by the red dots in the image below.
One way to solve this problem is to add a single pin component to the net. Create a component with a single pad that is the size of the vias being used in the design. If the branch point component pad is single-layer, then it can also be used in combination with a blind or buried via, by placing it on the via's start or end layer, giving complete flexibility as to how the routing is created. If you only want to include the branch point component on the PCB, set the branch point component's Type to Mechanical to exclude it from the BOM, and prevent any synchronization issues with the schematic. If you plan on including the branch point component on the schematic, the component Type can be set to Standard (no BOM).
Because the branch point is a node in the net, you can now define xSignals for just the trunk, for each major branch, and for each minor branch, if needed. These can then be used to scope matched length design rules, giving the designer complete control over how finely the length matching is to be performed.
The PCB panel includes an xSignals mode. Select it from the drop-down at the top of the panel to detail all xSignal Classes, xSignals, and their Primitives. The xSignals mode of the panel is used to examine and manage existing xSignals.
Right-click in the relevant section of the panel to perform xSignal related editing tasks, including:
When you click to select an xSignal in the panel, the design space display will dim, select or zoom based on the settings of these options at the top of the panel. If the xSignal is already routed, a thin line will be shown following the path that the software uses to calculate the xSignal signal length.
Select the xSignal in the panel then click the Delete button below the list of xSignals. Alternatively, right-click and select Delete from the context menu, or press
Delete on the keyboard.
The PCB editor includes a powerful and sophisticated filtering engine. This engine is used to identify objects when searching for objects in the design space, applying rules during interactive and automatic design tasks, and for checking rule compliance. The designer tells the filtering engine which objects they are interested in by writing a query, using query keywords recognized by the filtering engine.
The following xSignal type query keywords have been added for use in design rules and design space filters:
Design rules are how you translate your requirements into a set of instructions that the PCB editor can understand and obey. Rules can be checked during object placement, referred to as Online DRC, or as a post-process, referred to as Batch DRC. xSignals can be used to define the objects to which a design rule must be applied.
► Learn more about Design Rules
► Learn more about Length Tuning
The Matched Length design rule is used to ensure that the length of the specified nets is within the specified range. This rule is essential in a high-speed design, where the challenge is not just about how long it takes the signals to arrive (which is determined by their overall length), but how important it is that the specified signals arrive at the same. Depending on the signal switching speeds, the function of the signal, and the materials used in the board, the allowed difference could be as much as 500mils, or as little as 1mil.
The image below shows an example of the Matched Length design rule configured to target the xSignals in the xSignal class
PCIE, and test for a difference in lengths within each differential pair in that xSignals class. Each pair in the class
must have routed lengths that result in a Delay Tolerance of no more than
2ps delay between the two nets in that pair.
The image below shows the PCIE_TX xSignal class selected in the panel, and those xSignals selected in the design space.
The Length design rule is used to ensure that the overall routed length is within the specified range. This rule is typically used to ensure that the target nets are no longer than the specified length, for example, to ensure that the circuit timing requirements will be met. The length rule respects the xSignal type queries listed above.
The Return Path design rule checks for a continuous signal return path on the designated reference layer above or below the signals targeted by the rule. The return path can be created from fills, regions and polygon pours placed on a signal layer, or it can be a plane layer.
The return path layers are the reference layers defined in the selected Impedance Profile. Add a new Return Path design rule in the High Speed rule category.
The image below shows a Return Path rule violation, where the xSignal return path polygon has a hole for a via to pass through.
A key requirement of defining high-speed design rules is an accurate calculation of the route lengths. The traditional approach to calculating signal length is to add up the centerline length of all segments used in a route, as well as the vertical distance due to the height of the vias, which was originally determined by the board thickness.
This approach is not adequate for a high-speed design for a number of reasons, including:
The PCB editor's length calculator returns the most accurate route length possible.
In every high-speed design over 500 MHz, the connection medium, or bond wire to the die, introduces a delay to the signal. This in-device delay is referred to as the pin-package delay. Even if two devices are fully pin-compatible from a design and PCB standpoint, package flight times will be different across different devices, so they will need to be accounted for. Flight time information can be found within the IBIS 6 document for the device. The Package Pins information should be considered during the I/O planning stage, or after synthesis for an FPGA. All device manufacturers should be able to supply the package delays, which will be specified either as a picosecond delay or as a length.
The delay can be included in your design either as a Pin Package Length or as a Propagation Delay, using the respective fields for the pin in the schematic editor or the pad/via in the PCB editor. The values entered are handled as follows:
Pin Package Length - all pin package lengths within each net are added in the PCB editor to give the Total Pin/Package Length, which is included in the overall Signal Length for that net. Refer to the Nets mode of the PCB panel to learn more about the Signal Length.
Propagation Delay - all user-defined delay values defined for pins/pads and vias in each net are added to the routing delay for that net in the PCB editor. The routing delay is automatically calculated by the Simbeor® field solver built into the Layer Stack Manager. Pad and via delays are not calculated automatically but can be user-defined.
Pin package lengths can be defined as an attribute of the schematic component pin in the Properties panel in Pin mode. The software will default to use the Units of the underlying document, enter the units with the value, if required.
The Pin Package Length and Propagation Delay values are transferred to PCB layout as seen in the Pad mode of the Properties panel.
The Pin/Pkg Length is automatically included in the Signal Length calculations, which are displayed in various modes of the PCB panel. Set the panel to Nets mode to examine (or edit) the value of the Pin/Pkg Length for the pins in the chosen net. Note how the Routed Length column reflects the length of the routing, and the Signal Length column reflects the length of the routing plus any Pin/Pkg Lengths in that net.
In the image below the propagation Delay column shows that there are two pairs of xSignals that are failing a Matched Length design rule. Because the highlighting is in the Delay column, it indicates that the rule is configured to use Delay Units rather than Length Units.
The Pin/Pkg Length is automatically included in the overall xSignal length when:
In the PCB editor, the following terminology is used:
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