Altium Designer Documentation

Working with the Flight Time - Falling Edge Design Rule on a PCB in Altium Designer

Created: March 23, 2017 | Updated: September 26, 2019
All Contents

Rule categorySignal Integrity

Rule classification: Unary

Summary

This rule specifies the maximum allowable flight time on signal falling edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes for the signal on the net to fall to the threshold voltage (marking the transition from signal HIGH to signal LOW), less the time it would take for a reference load (connected directly to the output) to fall to the threshold voltage.

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Constraining the Design - Design Rules. For detailed information regarding how to target the objects that you want a design rule to apply to, see Scoping Design Rules.

Constraints

Default constraints for the Flight Time - Falling Edge rule.

  • Maximum (seconds) - the value for the maximum permissible flight time on the falling edge of the signal.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application

Batch DRC and during Signal Integrity analysis.

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