Altium Designer Documentation

Working with the Slope - Falling Edge Design Rule on a PCB in Altium Designer

Created: March 23, 2017 | Updated: September 26, 2019
All Contents

Rule categorySignal Integrity

Rule classification: Unary

Summary

This rule specifies the maximum allowable slope time on the falling edge of the signal. Falling edge slope is the time it takes for a signal to fall from the threshold voltage (VT), to a valid low (VIL). Constraints.

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Constraining the Design - Design Rules. For detailed information regarding how to target the objects that you want a design rule to apply to, see Scoping Design Rules.

Constraints

Default constraints for the Slope - Falling Edge rule.Default constraints for the Slope - Falling Edge rule.

  • Maximum (seconds) - the value for the maximum permissible falling edge slope time.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application

Batch DRC and during Signal Integrity analysis.

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