Altium Designer Documentation

Public Release Notes for PDN Analyzer

Created: October 18, 2016 | Updated: November 1, 2018

The following sections provide a running summary of the release notes for updates to the PDN Analyzer powered by CST® extension.

Version 2.0.2

Builds: 306 (for Altium Designer 17.1), 307 (for Altium Designer 18.0) and 309 (for Altium Designer 18.1)

Improvements:

22509 Improved current density uniformity at shape boundaries.
24918 Enabled docking of the PDN Analyzer panel by default.
24934 Reduced the default width of the simulation pane.
24938 Added batch analysis confirmation window.
24972 Allow a config to be opened after its PCB design was renamed.
24993 Improved network rendering for more complex topologies.
25188 Improved Highlight Peak Value "In View" mode behavior.
25189 Aligned Probe X, Y coordinates units with AD units.  

 

Bug Fixes:

24523 Corrected via mesh data for current density.
24636 Fixed bug related to layout changes not propagating to PDNA.
24639 Corrected engineering notation representation of some numerical results.
24649 Corrected Settings form window height.
24662 Corrected HTML report least margins results.
24664 Changed certain HTML report results representation to engineering notation.
24665 Auto-close HTML Report generation window.
24911 Fixed ODB++ export for pads with offset holes.
24913 Fixed bug that reported a VRM's max pin current in the max power column.
24914 Fixed bug in a selection of the bottom item in DC Nets list.
24941 Corrected erroneous HTML report classification of Prepreg layers as Core.
24944 Fixed a bug that limited the number of sequential VRMs to 1.
24971 Fixed a bug that disallowed the changing of a DC Net's nominal voltage.
25044 Corrected a bug that resulted in the omission of top layer data in the Vias tab.
25045 VRM Vout value of 0V is no longer allowed.
25061 Fixed an issue with the propagation of network voltages change to the block diagram.
25064 Corrected linear VRM output voltage in negative supply scenarios.
25071 Corrected erroneous results display on negative supply voltage networks.
25076 Fixed a bug that blocked the ability to disable via current limits.
25078 Fixed an excessive delay that resulted from changing min/max load limits.
25119 Corrected ODB export error related to negative plane thermal reliefs.
25208 Fixed latent display of newly added loads.
25510 Fixed "Index was out of range" bug in HTML report generation.
25568 Corrected the metal resistivity/conductivity calculator in the Settings form.
25714 Fixed bug related to "Object reference not set.." analysis error.
25798 Fixed VRM power dissipation calculation.
26142 Corrected the behavior of the load 5/10% tolerance buttons for negative network voltages.

 

Version 2.0.1

Builds: 253 (for Altium Designer 17.1) and 254 (for Altium Designer 18.0)

24002 Fixed bug where crash occurred when invoking or creating HTML report.
24003 Fixed simulation error: Can not find VIA vertices.
24004 Fixed a bug that caused a simulation error after tabbing out of a blank device parameter field.
24618 Corrected several minor typing errors in PDNA tooltips.
24543 Fixed unusually slow UI behavior on some installations.

Version 2.0.0

Altium has updated the PDN Analyzer extension by significantly enhancing its existing capabilities, adding numerous new features, and resolving issues and limitations in previous releases.

Builds: 244 (for Altium Designer 17.1) and 245 (for Altium Designer 18.0)

New features in version 2.0:

  • True simultaneous multi-network simulation
  • Multi-source support
  • Intelligent voltage regulator modeling, including sense line support
  • HTML report generation with image capture
  • Trace, shape, and via current/density limits
  • Visualization features, including
    • Voltage contour
    • Current direction indication
    • Peak value location
  • Detailed, sortable pin & via results
  • Automatic network power calculation

Significant changes:

  • Completely redesigned user interface:
    • More compact and productive layout
    • Integrated batch analysis and simulation messages tab
    • Support for increased network complexity
    • Detailed simulation results tables
    • Series element includes voltage drop parameter for diodes
    • Probe now supports differential voltage, current density, and via current
  • Improved accessibility when docked in Altium Designer

Resolved issues:

  • Mid-layer polygon planes disappearing when switching layer visibility
  • High series resistive element values producing unrealistic results
The PDN Analyzer powered by CST® runs on Windows 64-bit systems only.

Version 1.1.0

Note that this release requires Altium Designer 17.0, or later.

Build: 108 

Date: 3 May 2017 

16685 Fix bug that caused PDNA Batch Mode crashes with large simulation count.
17253 Fix bug that caused internal layer planes to disappear during results viewing.

Build: 95 

Date: 15 February 2017 

10723 Added support to display the voltage relative to the nearest ground when probing. Both the VCC and GND voltages are reported.
11329 Added ability to set up config files for many power rails and run them as a batch.
11868 Updated the battery symbol.
15160 The output .csv file now uses comma delimiters.
15161 Disabled unnecessary processing of Mechanical layers in ODB++
15162 Updated PDN Analyzer so ODB++ is only regenerated within a session if the layout changes.
15837 Added ability to navigate/zoom in on areas of highest current density.
16536 Fixed regression bug that caused mid-layer polygon object to not be displayed.
10696 When probing the signals, lose the ability to maneuver in 3-D (shift + right mouse doesn't rotate the image).

Version 1.0.0.64

Date: 22 August 2016

(Previously released version 1.0.0.63)

Altium and CST® have updated the PDN Analyzer extension. This version fixes cases where connections were missing between the pads of capacitors and their nets after simulation, and analysis was failing on a design due to meshing issues.

Version 1.0.0.63

Date: 20 July 2016

(Previously released version 1.0.0.62)

Altium and CST® have updated the PDN Analyzer extension. This version fixes cases where having semicolons (“;”) in components’ comments section caused a simulation failure.

Version 1.0.0.62

Date: 13 July 2016

(Previously released version 1.0.0.60)

Altium and CST® have updated the PDN Analyzer extension. This version fixes some cases where Version 1.0.0.60 could not load existing configuration files.

Version 1.0.0.60

Date: 7 July 2016

(Previously released version 1.0.0.46)

Altium and CST® have updated the PDN Analyzer extension to add new key capabilities, and resolve a number of simulation and interface issues. Below is a list of changes made to the current release of the extension and the issues that have been addressed.

1

New capability:

Added the ability to view voltages and current densities of vias.  Vias are now represented with appropriate color coding just as other power and ground shapes are.  Display of vias can be toggled as are layers.

2

New capability:

Added a ‘via wall thickness’ variable in the setup to comprehend vias as hollow objects.  The effective area of vias is derated appropriately to represent their increased resistance due to the missing material. See the Via Wall Thickness section of the documentation for more information.

3

Format change:

Improved the configuration file (*.pidc_confg) format by listing components with their full identifier, and not just by their reference designator. This is a significant change directed at making the Analyzer software more robust and capable, but will affect the portability of configuration files, since they will only be valid for the specific PCB from which they were generated.

4

Issues:

  • Improved reporting of simulation failures by providing more information about the cause, rather than just cryptic error codes.
  • Added preemptive disabling of simulations that will result in failures, when possible.
  • Resolved simulation failure on ‘PWR580B’ design using virtual components.
  • Resolved a Configuration loading issue where the changed ODB caused a virtual component mismatch.
  • Fixed Analyzer use of ODB layer names instead of user layer names.
  • Resolved customer design that fails for 0 thickness of ‘Plane2_1’, which doesn't exist.
  • Fixed updating of Recent Designs list, which did not include a config that has been saved under a new name.
  • Improved the separation of ‘Properties’ from ‘Criteria’ in the Source and Load selection dialog.
  • Resolved erroneously high current density being reported at connection to source.
  • Fixed layers not being shown for thick designs.
  • Resolved simulation failure when devices touch multiple power rails.
  • Fixed component selection, which prevented choosing the correct part if “j” has been typed after selecting the drop down.
  • Fixed Results panel not showing voltage results at load.
  • Resolved simulation failure when excitation has same pin designator for two pins.
  • Fixed wording when simulation fails from “Simulation ran failed…” to “Simulation failed…”.
  • Resolved simulation failure when multiple pins have been used on the source or load.
  • Separated the “Properties” from the “Criteria” better in source and load selection dialogs.
  • Fixed issue where the power path was made invalid when loading configurations.

Version: 1.0.0.46

Date: 23 May 2016

(Previously released version 1.0.0.43)

Altium has updated the PDN Analyzer extension to resolve an existing issue with designs which use the same pin designator for multiple pins. Below is detail of the issue addressed and changes made to the current release of the extension.

1

In previous versions of PDN Analyzer, using the same designator for multiple pins would cause the simulation to fail with the following (or similar) error messages:

  • [Error] <<error>>
  • [Error] solver stopped due to exception:
  • [Error] Traceback (most recent call last):
  • [Error]   File "<string>", line 1, in <module>
  • [Error]   File "altium_plugin\pidc.py", line 507, in create_plb_file
  • [Error]   File "altium_plugin\pidc.py", line 494, in create_ICs
  • [Error]   File "altium_plugin\pidc.py", line 455, in __init__
  • [Error] KeyError: ('1',)
  • [Error] <<end>>

This issue has now been resolved - simulations will complete successfully if the same pin designator is used for multiple pins.

Version: 1.0.0.43

Date: 13 May 2016

(Previously released version 1.0.0.42)

Altium has updated the PDN Analyzer extension to resolve an existing issue with designs which have spaces in their component names. Below is detail of the issue addressed and changes made to the current release of the extension.

1

In previous versions of PDN Analyzer, component names with spaces would cause the simulation to fail with the following (or similar) error messages:

  • [Error]    Flex_6946.PcbDoc    PDN Analyzer    solver stopped due to exception:
  • [Error]    Flex_6946.PcbDoc    PDN Analyzer    Traceback (most recent call last):
  • [Error]    Flex_6946.PcbDoc    PDN Analyzer      File "<string>", line 1, in <module>
  • [Error]    Flex_6946.PcbDoc    PDN Analyzer      File "altium_plugin\pidc.py", line 507, in create_plb_file
  • [Error]    Flex_6946.PcbDoc    PDN Analyzer      File "altium_plugin\pidc.py", line 494, in create_ICs
  • [Error]    Flex_6946.PcbDoc    PDN Analyzer      File "altium_plugin\pidc.py", line 360, in __init__
  • [Error]    Flex_6946.PcbDoc    PDN Analyzer    AttributeError: 'NoneType' object has no attribute 'n_pins'

This issue has now been resolved - simulations will complete successfully if net names have spaces in them.

Version: 1.0.0.42

Date: 11 May 2016

(Previously released version 1.0.0.37)

Altium has updated the PDN Analyzer extension to resolve existing issues and preclude analysis with invalid setup parameters.  One primary aim is to eliminate the possibility of performing a lengthy PDN Analyzer simulation only to find it was invalid due to an erroneous setup parameter.

Below is a list of the issues addressed and changes made to the current release of the extension.

1

Check that load has non-zero amperage: entering 0A as a current sink is now not allowed.

2

Ensure valid stackup before enabling simulation. Checks stackup parameters and disables simulation if any are not valid:

  • Invalid dielectric constant (<1).
  • 0 thickness for dielectric or conductor.
3

Ensure a maximum of 2 nets in the path between the source and load power nets.  If there are more than 2 nets between the source and load power nets, the user will be prompted by; “Many nets between source and loads, proceed with simulation?” (Yes, No).  This warns the user that they may have built an erroneous path (see Source to Load path section in the PDN Analyzer Guide).

4

Report the cause of any red exclamation marks (!), so as to inform the user what has failed. If a red exclamation mark is shown, the failure will be printed in the messages dialog:

  • "Error: Source <U#> exceeded max allowed PWR supply DC current magnitude. Allowed: x.xxxA, Actual: x.xxxA"
  • "Error: Source <U#> exceeded max allowed PWR pin current magnitude. Allowed: x.xxxA, Actual: x.xxxA"
  • "Error: Source <U#> exceeded max allowed GND pin current magnitude. Allowed: x.xxxA, Actual: x.xxxA"
  • "Error: Load <U#> did not meet minimum required DC Voltage magnitude. Minimum: x.xxxV, Actual: x.xxxV"
5

The maximum current densities reported by the auto-scale did not agree with maximum current density found when probing.  For example, auto-scaling showed the maximum current density as 1.2GA/m2, while probing indicated that the largest current density was 0.2GA/m2 (the internal .json file verified a maximum current density of 1.2GA/m2).  The software issue has been resolved, and probing now agrees with that reported by the auto-scale.

6

PDN Analyzer was not interpreting strings correctly: when converting the string "0Rab", if a is zero, the zero is discarded.  This is now resolved.

7

Older pcbdoc's do not have a SimulationDummy.PcbDoc.htm file, so the simulation failed. This issue has been fixed.

8

Collection of data on errors. If you have agreed to participate in the Altium Product Improvement Program, the following data will be collected:

  • If the simulation run was successful or not.
  • Error codes and messages.
  • Net count in the path, load count, source count, ODB file size, ODB++ generation time, and simulation run server time.
Found an issue with this document? Highlight the area, then use Ctrl+Enter to report it.

Contact Us

Contact our corporate or local offices directly.

We're sorry to hear the article wasn't helpful to you.
Could you take a moment to tell us why?
200 characters remaining
You are reporting an issue with the following selected text
and/or image within the active document: