回路設計の検証

Applies to Altium Designer version: 24

Schematic Validation and Configuring the Verification Options

To validate your design, choose the Validate PCB Project <ProjectName> command from the main Project menu. To validate the project focused in the Projects panel, you can also use the Validate Project command from the right-click menu of the project's entry or the  control at the top of the panel.

Validate your design using the Validate PCB Project &lt;ProjectName&gt; command.
Validate your design using the Validate PCB Project <ProjectName> command.

The software checks for logical, electrical, and drafting errors between the Unified Data Model and project checking settings. If validation errors and warnings are enabled for display on the schematic (enabled on the Schematic – Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel.

Use the controls associated with the Object Hints entry in the Connectivity Insight Options region (the System – Design Insight page of the Preferences dialog) to determine the launch style for object hints (Mouse Hover and/or Alt+Double Click).

There are a large number of drafting and electrical checks that can be performed on the validated design. These are configured as part of the project options. Select the Project » Project Options command from the main menus to open the Project Options dialog. The default settings will not suit every design and, therefore, it is important to become familiar with the options and how to configure them to suit your design.

When working with an Altium 365 Workspace project, note that the Workspace's Web Viewer includes the Electrical Rule Check report for the current project. This provides convenient access to ERC violations for review purposes without the need to access the design in Altium Designer. Learn more: Web Viewer – DRC and ERC Reports.

Drafting Checks

During validation, common drafting and editing errors are checked in accordance with the settings on the Error Reporting tab of the Project Options dialog. The error checks are organized in groups, for example, Violations Associated with Nets, Violations Associated with Components, etc. The groups are listed alphabetically in the dialog. The Report Mode of each violation can be changed to one of four values by clicking on it and selecting the desired value in the drop-down.

Configure the required error checks on the Error Reporting tab of the Project Options dialog. Click within the Report Mode cell of a violation to change it for this violation.
Configure the required error checks on the Error Reporting tab of the Project Options dialog. Click within the Report Mode cell of a violation to change it for this violation.

Generally, it is better to first validate the design and examine the warnings with the default settings. For those warnings that are not an issue for the current design, the reporting level can be changed.

See the PCB Design Violation Types section below for detailed information about each error check.

Connectivity Checks

The electrical connectivity is checked in accordance with the settings on the Connection Matrix tab of the Project Options dialog.

The Connection Matrix defines which electrical conditions are allowed and which are not allowed.
The Connection Matrix defines which electrical conditions are allowed and which are not allowed.

The matrix provides a mechanism to establish connectivity rules between component pins and net identifiers, such as Ports and Sheet Entries. It defines the logical or electrical conditions that are to be reported as warnings or errors. For example, an output pin connected to another output pin would normally be regarded as an error condition, but two connected passive pins would not.

Click on the small square in the matrix to change a particular rule. Each rule determines the reporting level for a given pin/net identifier combination. There are four possible values for each rule: Fatal Error, Error, Warning, and No Report.

The Error Reporting and Connection Matrix settings must be examined and set to suit the requirements of the current project.

Interpreting Messages and Locating Errors

When the project is validated, every condition that generates a warning or error is listed in the Messages panel. Note that the Messages panel will only open automatically if there is at least one Error or Fatal Error condition. To check for a Warning, you will need to open the panel manually by clicking the Panels button on the bottom-right of the design space then choose Messages. Once the project has been validated, the panel will list any warnings and errors that have been detected.

The Messages panel displays the warnings and errors detected in the project.
The Messages panel displays the warnings and errors detected in the project.

The Messages panel is command central for presenting violations. Things to be aware of include:

  • The Messages panel has two regions – the upper grid region summarizes the warnings/errors; the lower region gives details of the currently selected warning/error.
  • Double-click on a message to cross-probe to that warning/error. Double-click on a detail to show that specific object.
  • You can click on any of the Messages panel column headings (e.g., Class, Document, Message) to assist in sorting the errors and warnings.
  • Right-click in the Messages panel then use the Group By sub-menu options to group the errors and warnings by a specific criteria.
  • Right-click in the Messages panel then use the appropriate Clear command to delete messages or use the Export To Report command to export the messages to a report.

    Clearing messages does not necessarily mean the messages have been resolved. The same unresolved messages will be listed after performing validation again. Message clearance is a visual aid when resolving errors in the design that allows you to manually remove messages as you feel they have been resolved. Validation must be launched again to obtain an up-to-date picture of any violations that still exist.
  • The panel includes warnings and errors detected from settings in both the Error Reporting tab and the Connection Matrix tab.
  • When you right-click on a warning/error in the Messages panel then select the Place Specific No ERC for this violation command, you will automatically cross-probe to the error location and a No ERC directive will appear on the cursor, ready to place on the error location to suppress error checks. Learn more about Suppressing ERC Violations.

Resolving a Warning or Error

It is important to address each warning or error that is detected. The default error settings tend to be conservative since it is better for the software to err on the side of being cautious and let you decide if the testing boundaries can be relaxed. For example, your design may require IO pins to be connected to Input ports, requiring you to adjust the appropriate cell in the Connection Matrix tab. Another common error check to be changed is the Nets with no driving source, requiring you to disable that check in the Error Reporting tab.

There will be situations when you want to test the entire design for a certain condition, but you want to ignore a warning/error at a specific point in the circuit. For example, you might want to allow a net to be renamed at a specific location, but only in that location. This can be done by placing a No ERC directive at that location.

Suppressing ERC Violations

When you need to allow a specific point in the circuit to not report an error, place a No ERC (Electrical Rules Check) directive on that point meaning do not flag a warning/error at this location. Use a No ERC directive to deliberately limit error checking at a certain point in the circuit that you know will generate a warning (such as an unconnected pin) while still performing a comprehensive check of the rest of the circuit.

The No ERC directive supports a number of different styles and can be displayed in any color. Use this ability to reflect the design intent for this point in the circuit.

Choose a No ERC style that best reflects its function at that point in the circuit.
Choose a No ERC style that best reflects its function at that point in the circuit.

The No ERC directive has two modes of operation:

  • Suppress All Violations – in this mode, all possible warnings and/or error conditions are suppressed. The directive is often referred to as a Generic No ERC directive, in this mode.
  • Suppress Specific Violations – in this mode, only the selected warnings or error conditions are suppressed; any other warnings or errors will be detected and reported. The directive is often referred to as a Specific No ERC directive, in this mode.
Suppressed violations can be displayed in the Messages panel by enabling the Report Suppressed Errors in Messages Panel option, on the Error Reporting tab of the Project Options dialog. This feature can be used in the final stages of design to ensure that no critical errors have been inadvertently suppressed.
Note that No ERC directives cannot be used to suppress all types of error checks. When the No ERC dialog is in the Violation Types mode, it displays a list of the violation types that can be suppressed. Use this as a guide to learn which error tests can be suppressed.

Example Usage

How many times have you encountered a warning about a net 'not having a driving source', only to find that the message can be safely ignored? Perhaps an input pin is fed from a connector, the pin of which is nominally passive and the driving signal only present when an external cable is plugged in? Maybe the net is sourced from a pull-up resistor or switch, again passive in nature? One of the following strategies could be adopted to resolve this warning:

  • You could change the electrical characteristic of a source pin on the net. This is a fix rather than suppression, but as it involves a change to a pin's default mode of operation, it could create trouble further down the track. For example, consider wiring changes made to a design, in which the graphical display of pin direction is not enabled. Such changes might result in an output being connected to a pin of a passive device. If the pin of that device has been set electrically as an output (to alleviate previous driving source warnings), then you will have created a connection violation.
  • You could set the report mode for the associated violation check – defined on the Error Reporting tab of the Options For Project dialog – to No Report. This disables the check of this particular violation, but you would also not be able to catch any genuine errors elsewhere in the design.
  • The third (and arguably best) option is to place a No ERC directive on the net. You are not changing the design in any way, other than to suppress warning message 'noise' that you know is not a problem.

    Place No ERC directives on nets you know will cause 'no driving source' warnings.
    Place No ERC directives on nets you know will cause 'no driving source' warnings.

Placing a No ERC Directive

A No ERC directive can be placed into a schematic document in a number of ways:

  • Place a generic No ERC directive by choosing the Place » Directives » Generic No ERC command from the main menus, by clicking the button on the Wiring toolbar, or by right-clicking in the design space, and selecting Place » Directives » Generic No ERC command.
  • Place a specific No ERC directive on a point in the circuit that is already showing a violation, by right-clicking over a violating object in the design space (highlighted by a wavy colored line) and choosing the Place NoERC to Suppress command, from the context menu.

    Using the right-click context menu to place a specific No ERC directive.
    Using the right-click context menu to place a specific No ERC directive.

  • Place a specific No ERC directive on a point in the circuit that is already showing a violation, by right-clicking on a warning/error in the Messages panel, choosing the Place Specific No ERC for this violation command, then jumping straight to that point in the schematic and placing a No ERC directive configured to suppress that warning/error.

    Using the right-click context menu in the Messages panel to place a specific No ERC directive.
    Using the right-click context menu in the Messages panel to place a specific No ERC directive.

    The command will only be available if the message is a Net-related compiler violation.

Editing a No ERC Directive

During placement, and while the No ERC object is still floating on the cursor, the following editing actions can be performed:

  • From the Properties panel. This method of editing uses the associated Properties panel mode to modify the properties of an object.

    The No ERC mode of the Properties panel
    The No ERC mode of the Properties panel

    During placement, the No ERC mode of the Properties panel can be accessed by pressing the Tab key.

    After placement, the No ERC mode of the Properties panel can be accessed in one of the following ways:

    • Double-click on the placed directive.
    • Placing the cursor over the directive then right-click and choose Properties from the context menu.
    • If the Properties panel is already active, select the directive.
    The properties can be accessed prior to entering placement mode from the Schematic – Defaults page of the Preferences dialog. This allows the default properties for the object to be changed, which will be applied when placing subsequent objects.
  • From the No ERC dialog. This method of editing uses the No ERC dialog to modify the violation types and connection errors of a Specific No ERC object.

    The No ERC dialog showing Violation Types mode (the first image) and Connection Matrix mode (the second image) 
    The No ERC dialog showing Violation Types mode (the first image) and Connection Matrix mode (the second image)

    The dialog can be accessed by clicking Specific Violations in the Suppressed Violations region of the Properties panel in No ERC mode (mentioned above).

    The Specific No ERC directive can be configured to target multiple violations to support circuits that will generate multiple errors/warnings.
  • From the SCH List and SCH Filter panels. A List panel allows you to display design objects from one or more documents in tabular format, enabling quick inspection and modification of object attributes. Used in conjunction with appropriate filtering – by using the applicable Filter panel or the Find Similar Objects dialog – it enables the display of just those objects falling under the scope of the active filter – allowing you to target and edit multiple design objects with greater accuracy and efficiency.

A Generic No ERC directive can be quickly switched to be a Specific No ERC directive, and vice-versa, either through the Properties panel (in the Suppressed Violations section), or by toggling the Suppress Specific Violations property, on the SCH List panel.

Deactivating a No ERC Directive

Rather than deleting a No ERC directive, it can be made inactive (disabled in the eyes of validation). This state can be changed by toggling the directive's Active property – available through any of the methods of editing. An inactive No ERC directive will appear gray in the design space.

If you need to temporarily remove use of a No ERC directive, render it inactive, rather than deleting it.
If you need to temporarily remove use of a No ERC directive, render it inactive, rather than deleting it.

Controlling the Printing of No ERC Directives

By default, No ERC markers are included during printing. To control this by either disabling their inclusion entirely or excluding only specific symbols, use the Print dialog as shown below.

Control the printing of No ERC markers in the Print dialog.
Control the printing of No ERC markers in the Print dialog.

PCB Design Violation Types

Violations Associated with Buses

Violations Associated with Components

Violations Associated with Documents

Violations Associated with Harnesses

Violations Associated with Nets

Violations Associated with Others

Violations Associated with Parameters

注記

利用できる機能は、Altium Designer ソフトウェア サブスクリプション のレベルによって異なります。

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