This rule tests the completion status of each net that falls under the scope (full query) of the rule. If a net is incomplete then each completed section (sub-net) is listed along with the routing completion. The routing completion is defined as:
(connections complete / total number of connections) x 100
The PCB Editor's Design Rule Checking system typically sees a net as being routed if all nodes in that net (component pads) are connected through the use of net-aware design objects (tracks, arcs, pads, vias, and polygons). These objects are considered connected if they touch each other. However, while simply touching makes a perceived connection to the software, when it comes time to fabricate the board, the fragility of some of these 'connections' can cause critical issues, especially where the objects - for example two contiguous track segments, or a track entering a pad/via - are only slightly touching. Such connections are often referred to as 'Bad Connections', 'Poor Connections', or 'Incomplete Connections'. This rule can also be configured to test for such poor connections.
Check for incomplete connections - with this option enabled, the following additional checks on connectivity between applicable design objects are made:
Track/Arc to Track/Arc - checking that the centerlines, or centers of the ends of the connecting track/arc segments, coincide.
Track/Arc to Via - checking that the centerline, or center of the end of a track/arc segment, is placed on the shape of the via.
Track/Arc to Pad - checking that the centerline, or center of the end of the track/arc segment, is placed on the shape of the pad.
Via to Pad - checking that the center of the via is placed on the shape of the pad.
Via to Via - checking that the centers of the two vias coincide.
Polygon to Track/Arc - checking that the center of the end of a track/arc segment is overlapped by the polygon.
Polygon to Pad/Via - checking that the center of the Pad/Via is overlapped by the polygon.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.
A poor connection will be flagged in the design space using the detailed violation marker,, with a corresponding message appearing in the Messages panel.
Where applicable, a connection line will be drawn between unconnected objects in the net, with data regarding the un-routed net length reflected in the PCB panel (in Nets mode).
Some split plane DRC checks require the Un-Routed Net rule to be Batch-enabled for them to work.
In Printed Electronics, layer transitions do not require a via, the net analyzer will recognize that the net is not broken if a via is removed from a routed net. A board is defined as Printed Electronics when the Printed Electronics option is enabled in the Layer Stack Manager. Learn more about Printed Electronics.