With increasing device switching speeds, controlled impedance routing has become the hot topic for the digital designer. This article will introduce how you can use the Signal Integrity analysis engine to match component impedances, and the controlled impedance routing capabilities in the PCB editor.
There is a saying bandied about in engineering circles - there are only two kinds of electronics engineers working in digital design: those who have had signal integrity problems, and those who will. Not so many years ago the term signal integrity was one for the specialist, you only had to deal with it on high speed designs. But the device switching speeds in those high speed designs are no longer anything special, in fact they are rapidly becoming the norm. As improving integrated circuit technology drives the size of the transistor down, the speeds at which they can switch goes up. And it is this switching speed that affects the integrity of digital signals.
Thankfully many potential signal integrity issues can be avoided by following good design principals, and implementing the design as an controlled impedance board. Achieving this does require specific design tool capabilities - you need analysis tools that can detect nets with potential ringing and reflection issues, and board design tools that allow the designer to achieve the correct routing impedances. Altium The PCB editor has these capabilities.
This article will help you understand what causes signal integrity issues, and if your board is likely to suffer from them. It will also discuss the two design approaches you must employ to minimizing potential SI issues - matching component impedances, and controlled impedance routing.
Do I need to bother with controlled impedance routing, you ask?
In an ideal situation all of the energy that comes out of a component output pin would be coupled into the connected track on the PCB, flow through the PCB routing to the load input pin at the other end, and be absorbed by that load. If all the energy is not absorbed by the load then the left over energy can be reflected back into the PCB routing, flowing to the source output pin. This reflected energy can interact with the original signal, adding to and subtracting from it (depending on the polarity of the energy), resulting in ringing. If the ringing is large enough it will affect the integrity of the signal, resulting in unpredictable, erroneous circuit behavior.
And how do you know if this might occur? If the source pin is able to complete its edge transition before the signal reaches the load pin, then the conditions exist for your design to be impacted by reflected energy. A common rule of thumb that is used to determine if SI issues are likely is the "1/3 rise time" rule. This rule states that if the trace is more than 1/3 of a rise time long, reflections (ringing) can occur. If the source pin has a 1 nSec rise time, then a route longer than .33 nSec - which is approximately 2 inches in FR4 - must be considered to be a transmission line, a candidate for signal integrity issues. If your devices have this sort of rise time and you know you will have routing of this sort of length, then you might well end up with signal integrity issues on the PCB.
So how do you avoid this situation where there is energy being reflected back and forth between the source and the load - you avoid it by matching the impedances. Impedance matching insures that all the energy is coupled from the source into the routing, and then from the routing into the load. Routing the board with regard to the impedance is referred to as controlled impedance routing, or another way of saying it is that a board where impedances have been managed is called a controlled impedance PCB.
There are two distinct elements to achieving impedance matching: the first is matching the components; and the second is routing the board to give the required impedance.
You cannot achieve a controlled impedance PCB with routing alone. Firstly you must check, and if necessary, match the impedances of the components.
Ideally you want to detect nets that could have potential signal integrity issues during the design capture phase, so that any additional termination components can be included before the board design process starts. And since output pins are low impedance and input pins high impedance, it is likely that you will need to add termination components to the design to achieve impedance matching.
You can perform a signal integrity analysis on your design at the schematic capture stage. If you do (Tools menu), you will be prompted to provide an average track impedance and route length, and define the supply nets. Once this is done the design can be analyzed, and any potential problem nets identified in the Signal Integrity panel, as shown below.
From the panel you can perform a reflection analysis on selected nets. You can also experiment with possible termination configurations and values, note that the Termination region of the Signal Integrity panel shown in the image above has the Serial Res option enabled. The section of the panel just below that shows a series termination resistor, this is where you define the minimum and maximum series termination resistance values that will be used for the reflection analysis (disable the Suggest checkbox to enter your own values).
The images below show two graphs of a net displaying ringing. The first is the net without termination, the second with the theoretical series termination resistance included at the source pin.
Ten passes of the reflection analysis were performed, with the theoretical terminator stepping from 20 ohms to 60 ohms. The 5 passes (first sweep at 20 ohms, last sweep at 60 ohms) are listed down the right-hand side of the graph, clicking on each highlights that result, and displays the theoretical termination resistance value at the bottom right. For this net, a series termination resistance of 40 ohms would produce the graph selected in the image on the right.
The second part of achieving a controlled impedance PCB is to route the board so that the tracks are a defined impedance. There are a number of factors that influence the impedance of your signal routing, including the physical dimensions and properties of the materials used to fabricate the PCB.
Below are the two formulas that the software uses to calculate the routing impedance, the appropriate one being selected depending on whether the route has a plane layer present on only one side of it - referred to as a microstrip, or has planes present on both sides - referred to as a stripline. Note that if the plane layer(s) are not adjacent to the signal layer then the nearest plane layer(s) will be used in the calculations. Note also that an offset stripline configuration is not supported.
Microstrip characteristic impedance formula
Zo=(87/SQRT(Er+1.41))*LN(5.98*TraceToPlaneDistance/(0.8*TraceWidth + TraceHeight))
Stripline characteristic impedance formula
Zo=(60/SQRT(Er))*LN((1.9*PlaneToPlaneDistance)/(0.8*TraceWidth + TraceHeight))
From the formulae you can see that the copper and insulation (dielectric) thicknesses, the routing width, and the Er all contribute to the impedance. Er is the dielectric constant of the dielectric material, for the standard fiberglass dielectric most commonly used in PCB fabrication (FR-4) this can vary by up to 20%, over the range of 4 to 5. There are other more stable dielectric materials available, such as polyimide and Teflon.
As you can see from the formula there are many inter-related values that contribute to the routing impedance. To complicate matters, as the board designer you have to consider these requirements alongside the normal tradeoffs you have to make - such as selecting the most appropriate routing widths / clearances and minimizing the layer count to meet the project budget.
Ideally you will have an impedance that you have been asked to achieve, typically something in the range of 40 to 90 ohms. Rather than you needing to calculate the routing width for each layer so that you can achieve the specified impedance, you can specify the impedance, and the software will calculate the routing width required on each layer to achieve this.
To do this, enable the Characteristic Impedance Driven Width option when you are setting up the Routing Width design rule in the PCB Rules and Constraint Editor, then enter the required minimum/preferred/maximum impedances - these will automatically be translated into widths for each signal layer. A six layer (4 signal + 2 plane) example is shown in the image below.
As you route the board and change layers, the software will automatically adjust the track width to the size needed to achieve the specified impedance. This interactive controlled impedance routing greatly simplifies the task of designing a controlled impedance PCB.
Note that the built-in impedance calculator does not account for the affect of vias, it assumes lossless transference from one signal layer to the next. Additionally, it only takes into account single-ended structures (not differential), and determines the routing width of target nets on a whole-layer basis.
A fundamental requirement for controlling the impedance is to include power planes that can provide a signal return path below each signal path. These planes should be distributed through the board stackup, ideally they are arranged so that there is at least one plane adjacent to each signal layer that is carrying controlled impedance routing. The adjacent plane provides each signal return path, and for reasons that will not be covered here, does so regardless of the DC voltage distributed by that plane.
The return path current flowing through the plane will attempt to follow the same physical path as the route on the signal layer, so it is important to always try to avoid introducing discontinuities, such as a split or blowout in the power plane, underneath any critical routing.
As well as the selecting a suitable order for signal and plane layers, you also need to define the material properties of each layer, including:
These values, and the routing width, all contribute to the final impedance. Achieving the required impedance then becomes a process of tuning all these values. Keep in mind that possible copper and dielectric thickness values may be limited too, determined by the materials available from your PCB fabricator.
For example, typical values of copper thickness used are 0.7mil (18µm or 1/2 oz) for signal layers, and 1.4mil (36µm or 1 oz) for plane layers. But if your stackup is such that one signal and one plane layer are a pair on either side of one of the original thin panels used in the multilayer process, then they may need to have the same copper thickness.
In the previous images, the internal copper is 36µm and the outer copper foil layers are 18µm. The dielectric layers are all 250µm.
The problem with this stackup is that to achieve 50 ohm routing, the width required on the top layer is 396µm (approx 18mil), which is quite a wide route.
One solution is to reduce the dielectric thicknesses. In the images below, the thicknesses of
De2 have been reduced to 120µm. This has reduced the top layer (
Cu1) routing width to 207µm (approx 8mil), and the
Cu3 (Sig) layer routing width to (5mil). Both of these widths should be suitable for routing to most components.
Like copper thickness, core thickness will only be available in specific increments, since the core thickness is defined by the thickness of the layer-pair panel used in the multilayer process. You will probably have greater freedom with prepreg thicknesses. And then there is the overall final board thickness, this must also be a realistic value (around 62mils is typical).
From this simple example you can see that there is a process of working from available materials and desired impedances to arrive at the final board stackup and routing widths.
In the same way that you tested the nets during design capture using an assumed routing length and routing impedance, once the routing is complete you should repeat this process on the board to check for potential impedance mismatches and reflection issues. Launch the Signal Integrity command from the PCB editor Tools menu. Since the PCB is part of the project, the material properties and dimensions defined in the Layer Stack Manager and the actual widths of the routes on the board will be used to calculate the impedances used for the signal integrity tests.
Beyond the iterative dimension tuning process that you go through to achieve the correct impedances, there are other factors that influence the final impedance that will be achieved on your fabricated PCB. These include the consistency and stability of the dielectric material used in the PCB, and also the consistency and quality of the etching process. If you require a controlled impedance PCB you should discuss this with your PCB fabricator. Some fabricators can advise on track geometries if you supply them with your preferred stackup. Many will also be able to include an impedance test coupon on each panel that they fabricate - this can be used to measure the real impedances achieved on the board.
This article gives an introduction to the topic of signal integrity and controlled impedance PCB design. Use the following links to learn more, where you can access resources developed by recognized industry experts.