Rule category: Electrical
Rule classification: Binary
This rule defines the minimum clearance allowed between any two primitive objects on a copper layer. Either a single value for clearance can be specified, or different clearances for different object pairings, through use of a dedicated Minimum Clearance Matrix. The latter, in combination with rule-scoping, provides the flexibility to build a concise and targeted set of clearance rules to meet even the most stringent of clearance needs.
Different Nets Only- constraint is applied between any two primitive objects belonging to different nets (e.g. two tracks on two different nets).
Same Net Only- constraint is applied between any two primitive objects belonging to the same net (e.g. between a via and pad on the same net, or within the same track of a differential pair).
Any Net- constraint is applied between any two primitive objects belonging to any net in the design. This is the most comprehensive of the three options and covers the possibility of the objects belonging to the same net or different nets.
For many users, there is no great difference between Track and Arc primitives. And when it comes to Fill, Region, and Polygon objects, most users just see these as more 'copper.' With this in mind, the minimum clearance matrix for the Clearance rule has been enhanced to operate in two modes:
Definition of clearance values in the matrix can be performed in the following ways:
With the required selection made (either a single cell or multiple cells), making a change to the current value is simply a case of typing the new value required. To submit the newly entered value, either click away on another cell, or press Enter. All cells in the selection will be updated with the new value.
Designers can check clearances between the edges of drill holes and neighboring copper objects on signal layers. This is particularly beneficial in preventing the routing of track too near to a drilled hole, which could otherwise suffer from any potential wandering of the drill during board fabrication. The row at the bottom of the Clearance rule's minimum clearance matrix is used to define the desired clearances.
Designers can also check clearances between split plane regions on internal plane layers. How clearance is defined depends on the mode in which you are using the minimum clearance matrix:
A violation will appear in the form:
Clearance Constraint: (<CurrentClearance> < <DefinedClearance>) Between Split Plane (<NetName>) on <InternalPlaneLayerName> And Split Plane (<NetName>) on <InternalPlaneLayerName>,
Clearance Constraint: (32.36mil < 34mil) Between Split Plane (GND) on Internal Plane 1 And Split Plane (NetC6) on Internal Plane 1
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expressions match the objects being checked.
Online DRC, Batch DRC, interactive routing, autorouting, and during polygon placement.
Different Nets Only. An example of when
Same Net Onlyor
Any Netcould be used is to test for vias being placed too close to pads or other vias on the same net, or any other net.
InPoly) should be included in the Full Query in this case, instead of
IsPoly). The specific polygon clearance rule must also be given a higher priority than any general clearance rule, if it is to have any effect.
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