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Parent page: Advanced Design Technologies
The purpose of this article is to introduce the key elements of high-speed design and then discuss how each of those elements is tackled in Altium Designer. This article does not attempt to provide a complete discussion of high-speed design; for that, there are a number of highly experienced and scholarly designers and engineers that have written excellent reference papers and books on the subject. Refer to the References section for links to these authors, and the papers used during research for this article.
So exactly what makes a PCB design a high-speed design? Sure it’s about things happening quickly, but it’s not just about the clock rate used on the board. A design is a high-speed design when it includes devices with fast edges - devices that switch state so quickly that the transition is complete before the signal can travel along the route and reach the target pin. In this situation the signal can be reflected back to the source pin, degrading or destroying the original signal data. A signal with a fast edge can also radiate from the route and couple into adjacent routes, or radiate further and become electromagnetic interference (EMI), resulting in the product failing to meet mandatory emission standards.
When a signal has fast edges, it changes the way that the energy travels through the routing. In a circuit where edge rates change slowly, you can think of the energy flowing through the routing like water through a pipe. Yes, some energy is lost due to friction as the water is pushed through the pipe, but basically most of it arrives at the other end. For a DC or low switching frequency circuit you can work out the resistance of the route and make sure that the amount of energy lost along the way does not affect the circuit performance.
It's not so simple in a high-speed design because as well as the energy flowing as electrons through the routing copper, in a fast-switching signal, some of that energy also travels as electromagnetic energy around the routing copper. Now you are no longer designing copper pathways for electrons; you're designing a series of transmission lines embedded in a printed circuit board.
As the switching speed of the edge increases, the energy traveling through a route behaves differently. It no longer travels like water inside a pipe. instead, most of the energy is concentrated at the very surface of the route (known as the skin effect), with a portion of the energy actually traveling as electromagnetic radiation. Not traveling through the actual conductor, this electromagnetic energy travels through the material surrounding the route. Like dragging your foot through water, when energy travels in this way the signal actually slows down. Now it is the properties of the material around the route that dictate how quickly the signal travels and how much its arrival will be delayed.
So when does this become a problem, the time it takes for the signal to propagate down the route to the target pin? Like a wave hitting a wall, when the signal arrives at the target input pin some of the energy in the signal is reflected back towards the source pin. If this reflected energy arrives back at the source pin while the original signal edge is still transitioning, the original signal will be strong enough to swamp the reflection as it completes its transition and your signal will be OK. But if the edge transition is completed before the reflected energy arrives back, like an echo in the canyon, that reflected energy will interact with the original signal and change it, perhaps so much that you cannot work out what was actually shouted into the canyon.
To summarize, when the travel time along this round-trip length is equal to or longer than the rise time of the signal, the integrity of that signal is in doubt and your design is now a high-speed design! The length of that route is referred to as the critical length - routes shorter than this should not experience signal integrity issues, whereas routes longer than this might.
To analyze your design, a common rule of thumb that is often used is the 1/3 rise time rule, which states that if the route is more than 1/3 of a rise time long, reflections can occur. For example, if the source pin has a 1 nSec rise time, then a route longer than .33 nSec - which is approximately 2 inches in FR4 - must be considered to be a transmission line and therefore a candidate for signal integrity issues.
Assuming the Dielectric Constant εR of FR4 is 4, the Velocity of a Signal in FR4 is given as:
Vp(FR4) = (299.792458 / √4) mm/ns
=149.89 mm/ns (approx 6 inches/ns)
For FR4, the route length at which transmission line effects need to be considered can be calculated as:
LR ≥ TR × 49.965 mm
If TR = 1nS
LR ≈ 50mm (2 inches)
If TR = 100pS
LR ≈ 5mm (0.2 inches)!! On a board with signals switching at these speeds, most routes will be transmission lines.
Since it is not possible to ensure that all routes are shorter than the critical length, how do you ensure that the information encoded in your signals is received correctly, and not swamped by reflections? You do that by minimizing the amount of energy that is reflected back. Ideally, you want all of the energy that arrives at the target input pin to pass through into that component and none to be reflected back. Just how do you get that to happen?
To prevent reflections, you need to think of and design the route as if it is a transmission line. Why? Because a transmission line has the special behavior that when it is terminated by an impedance the same as its own impedance, no energy is reflected. Now you have a method of handling those routes that are longer than the critical length; route them as a transmission line. This means you route them so they have a specific impedance, then terminate them with the same impedance.
The impedance of the routing is defined by the dimensions of the routing (the width and height of the pipe), and the properties and dimensions of the surrounding materials, which will be the surrounding air or dielectric layers. To function as a transmission line, the layer that is adjacent to the signal layer must be a plane layer. By carefully arranging the layers in the layer stack and calculating the dimensions and properties, a specific impedance can be achieved for the routing. This approach to routing is referred to as controlled impedance routing, where the target impedance is kept constant, and the material dimensions and properties are selected and adjusted to achieve that.
A controlled impedance PCB cannot be achieved through routing alone though. There are two pieces to this puzzle - controlling the impedance of the routing, and matching that impedance to the pins in the net. Achieving this matching often requires the addition of termination components. Terminations can be added close to the source pin, or close to the target pin. A good approach to working out if a high-speed net needs terminating is to analyze the design with a signal integrity simulator. Unlike a circuit simulator, which models and simulates the behavior and interaction of the components, a signal integrity simulator models the behavior of the routing and its interaction with the component pins. For signal integrity simulation the components are only modeled in terms of the I/O characteristics of their pins.
The signal integrity analysis tool needs to:
But wait, there’s more (or is that Moore?). Electrical energy only flows when there is a closed-loop, so the energy flowing out along the signal route must also have a return path. This return path is typically provided by the ground routing that has to provide a return path for all of the signals in the design. There’s an interesting phenomenon that occurs with signals with fast switching edges. The returning energy of a signal wants to flow back along the same twisting and turning path that the signal route took across the board. Why? Because this is the path of least impedance for that signal. Even though it could flow the shortest distance from the target component back to the source component, it does not.
So as well as thinking about the routing path for the signal, you also have to ensure there is an unbroken path for the return current immediately under the signal route. If the return energy has to deviate from below the signal path to get around an obstacle, like a hole in the plane (a blowout), then a loop is created. The loop is the gap between the two paths as you look down into the board, and the area of this loop is proportional to the amount of energy that will now be radiated by this signal. If there is a blowout in the plane that is unavoidable, consider rerouting the signal trace to suit the return path, as reducing the loop area is generally considered more important than minimizing the route length.
Modern signaling technologies, such as differential pairs, help reduce the need for a high-quality return plane by routing the signal path and the return path together as a pair, ensuring that they are closely coupled in both separation and overall length. As well as the strong coupling and the reduced reliance on a high-quality reference ground, differential pairs offer another big advantage - excellent immunity to noise.
The electromagnetic energy that is traveling around the route as part of each signal does not all couple into the target input pin; some of it escapes and interferes with adjacent signals. This escaped energy becomes what is called electromagnetic interference (EMI), and when it couples into a neighboring signal, it creates what is called crosstalk. Differential pairs are good at coping with crosstalk because the radiated energy couples into both the outgoing signal and the return signal, creating what is called common-mode noise (the noise is common to both signal paths). If there was only a single signal, this crosstalk would add to that signal and distort it. But the differential pair input pins are designed to look at the difference between the pins in the pair, and so are able to reject the common-mode noise.
These two qualities - the ability to closely match the lengths of the signal and its return path, and the ability to withstand the effects of crosstalk - make differential pairs the preferred solution for high-speed signaling, which can support data rates beyond 10 Gb/s on a PCB.
If carefully controlling the impedance and insuring there is a high-quality return path are the first two edges of the high-speed design triangle, vias are the third edge of that triangle. At low frequencies, a via has little impact on the signal quality and can be used without consideration of its impact on circuit performance. However, if your design is functioning as a high-speed design, the vias can impact on the circuit performance and the signal quality.
Vias appear as both capacitive and inductive discontinuities, so their presence affects the impedance of the signal route. As well as affecting the impedance, unused via barrel length presents as a stub which can create reflections. Quantitative studies have shown that their impact can be reduced by addressing each of the following areas:
Another approach to minimize the impact of vias in a high-speed design is to use microvias. A microvia is a small via. IPC standards (IPC/JPCA-2315 and IPC-2226) define microvias as blind or buried vias with a diameter equal to or less than 6 mils (0.15 mm). A 6 mil diameter is at the limit for mechanical drilling so microvias are typically laser-drilled. There are also hybrid laser modified + controlled depth mechanical hole drilling techniques used, as outlined in this paper, which offers advantages in fabrication.
Microvias offer a number of advantages:
Because some of the energy in a high-speed signal travels through the material that surrounds the route, it is inevitable that some of that energy will couple into adjacent routes. Referred to as crosstalk, this energy will degrade the quality of that signal. In signal integrity language, the signal that is radiating the energy is referred to as the aggressor net, and the signal that is receiving the crosstalk energy is referred to as the victim net. So how do you reduce the amount of energy that escapes from the aggressor, and how do you reduce how much of that energy is coupled into the victim? The basic approach is to reduce the amount of energy escaping from the aggressor route through impedance matching and correct design of the signal return path, and to keep potential victim nets away from aggressors.
Clock signals and other periodic signals are the prime sources of crosstalk in a design. An often-used rule of thumb is to ensure that potential aggressors, such as clocks, are separated from potential victims by three times the width of the routing (measured center to center). This is known as the 3-W rule. Or in edge-to-edge terms, the separation must be no less than twice the routing width. This is a large clearance, so you will need to be selective about the nets to which it is applied. High-threat aggressors, such as clocks, are one group. The other main group to consider is the more sensitive potential victims, such as differential pairs; this group also benefits from a pair-to-other-signal separation of 3-W.
Last but not least, there is the time it takes for the signal to arrive at its destination input pin. Generally, a signal does not exist in isolation. It is working in harmony with a multitude of other signals. A simple example would be the 8 bits in a byte of data. Not only must the entire byte arrive within the time allowed, the bits within the byte must all arrive together too. The time it takes for a signal to travel from output to input is referred to as the flight time, and any difference between the arrival times of the bits is referred to as the signal skew.
The key factors that influence both the flight time and the skew are:
Managing these requires consideration of:
All of this happens on the printed circuit board. Since they were first created in the 1940s, the humble PCB has undergone tremendous levels of refinement in fabrication technology and materials. This has lead to enormous reductions in the size of the features, including the routing and vias. Tracks are no longer fabricated at 20 mils wide. Now they can be as small as 2 mils wide; and a small via is no longer 30/18 mil (land/hole) - it is 12/6 mil. A new name was created to describe designs using features this small - High-Density Interconnect (HDI) techniques. While it costs more to create the smaller features used on HDI boards, their smaller size means the finished design can use fewer layers, have shorter routes, and improved signal integrity, which can ultimately result in a board that might not cost any more to make (but can be much harder to test and repair).
A large part of the challenge with a high-speed design is managing the medium that the signals travel through. Traditional FR4 has provided a cheap and effective board substrate material for decades, but the non-homogenous structure of fiberglass weave embedded in resin becomes a limiting factor for high-speed designs. The resin has a different dielectric constant (≈3) from the fiberglass weave (≈6), and since the fiberglass is a woven structure with gaps in the weave, the signal sees a changing dielectric constant as it travels across the board. Because of this, there is a range of FR4 materials available. Better materials have a tighter weave structure that gives a more consistent dielectric constant. The dielectric constant of FR4 also changes with temperature by as much as ± 20%.
There are superior materials available for PCB fabrication, such as Teflon or ceramic, but these come at a price. The material that the board is fabricated from must be considered and chosen early in the PCB design process in consultation with the fabricator. To help balance material selection against material cost, many PCB fabricators allow a mix of materials so that the expensive materials are only used for the layers that carry the high-speed signals.
Like many aspects of printed circuit board design, working out the best number of layers is as much art as it is math. Fanout and escape routing of dense BGAs will strongly influence the number of routing layers. Performing a test fanout and escape route to check the densest BGA in the design can help verify there are enough signal layers. Another approach, recommended by Barry Olney of In-Circuit Design, is to run a test autoroute on the board. He suggests that if it completes at least 85% of the routes, the board should be hand-routable using the current layer stackup.
Adding and assigning layers is done in pairs. Generally, you will either have a pair of plane layers for each pair of signal layers, or a pair of plane layers for every two pairs of signal layers. So a four-layer board will be two plane and two signal; a six layer board will be two plane and four signal, an eight-layer board will be four plane and four signal, and a ten layer board will be four plane and six signal layers. Note that this is only a guideline; the overriding objective is to ensure that every high-speed signal layer is adjacent to a plane layer.
Not all signals are high-speed signals, and not all layers can be configured as high-speed routing layers, so the standard practice is to assign and route the high-speed signals on specific layer pairs. Each signal layer pair should have one layer in the pair assigned for vertical routing and the other assigned for horizontal routing, and these should be followed as best as possible to reduce crosstalk between the adjacent layers. The high-speed pair can be positioned on either side of a plane layer or between two plane layers.
The thickness of the dielectric between the high-speed signal layers and the reference plane layer will be set to suit the required characteristic impedance; typically this will be less than 10 mils (0.25 mm). To achieve the overall board thickness required for mechanical reasons, adjust the thickness of a dielectric layer(s) that is not adjacent to a high-speed signal layer, for example, the center core layer.
The table below shows a number of possible layer stackups and layer assignments. The arrangement of high-speed pairs and general purpose pairs can be changed, for example, if your six-layer/thruhole-only design can have the high-speed signals routed on the top layer, this is a good option if it means the high-speed signals do not need to use vias. Keep each high-speed layer adjacent to a plane layer, and the surrounding dielectric thicknesses the same for the high-speed layers.
|Signal HS-H||GND||Signal HS-V|
|Signal H||GND||Signal HS-V||Signal H|
|Signal V||GND||Signal HS-V||Signal H||GND|
|GND||Signal HS-V||GND||GND||Signal V|
|POWER||Signal HS-H||POWER||POWER||Signal H|
|Signal H||POWER||Signal H||Signal V||POWER|
|Signal V||GND||Signal HS-H||Signal V|
|Signal V||GND||Signal HS-H|
This section provides information on how to tackle each of the challenges in designing a high-speed PCB, in Altium Designer.
To summarize, the process of routing a board with high-speed signals requires you to manage:
Early in the design process, it is important to identify signals that might require impedance matching so that additional termination components can be included before the component placement process is complete. Since output pins are typically low impedance and input pins are typically high impedance, termination components may need to be added to the design to achieve impedance matching.
Altium Designer includes a signal integrity simulator that can be accessed during both the design capture and board layout phases of the design process, allowing both pre- and post-layout signal integrity analysis to be performed (Tools » Signal Integrity). The signal integrity simulator models the behavior of the routed board by using the calculated characteristic impedance of the traces combined with I/O buffer macro-model information as input for the simulations. The simulator is based on a Fast Reflection and Crosstalk Simulator, which produces very accurate simulations using industry-proven algorithms.
Because both design capture and board design use an integrated component system that links schematic symbols to relevant PCB footprints, SPICE simulation models and signal integrity macro-models, signal integrity analysis can be run at the schematic capture stage prior to the creation of the board design. When no board design is present, the tool allows you to set up the physical characteristics of the design, such as the desired characteristic trace impedance, from within the signal integrity simulator. At this pre-layout stage of the design process, the signal integrity simulator cannot determine the actual length of particular connections so it uses a user-definable average connection length to make its transmission line calculations. By carefully choosing this default length to reflect the dimensions of the intended board, you can gain a fairly accurate picture of the likely signal integrity performance of the design.
Nets with potential reflection problems can be identified and any additional termination components can be added to the schematic before proceeding to board layout. The values of these components can then be further tuned once the post-layout signal integrity analysis has been performed.
► Learn more about Impedance Matching the Components
High-speed design is the art of managing the flow of energy from one point on a circuit board to another point. As the designer, you need to be able to focus your attention and apply the design constraints onto a signal that travels from this point on the board to that point on the board. This signal you are focusing on is not necessarily a single PCB net though. The signal might be one branch of A0 in a design that you intend to route in a T-branch topology, with the other branch of A0 being another signal you need to focus your attention on as well, and be able to compare the route lengths of these two signals. Or the signal might include a series termination component in its path (which the PCB editor sees as one component and two PCB nets), and if that signal is in a differential pair, its length needs to be compared to the length of the other signal in that pair.
You can manage these requirements using a feature known as xSignals, where an xSignal is essentially a user-defined signal path. You select the source pad and the target pad (in the workspace or in the PCB panel) then right-click on either to define that signal path as an xSignal. As well as interactively defining an xSignal by its start and end pads, you also can run the intelligent xSignals Wizard, whose heuristics will help you to quickly set up a large number of xSignals between the chosen components. These xSignals can then be used to target design rules to your high-speed signals. The software understands the structure of these xSignals; for example, calculating the overall length of multiple nets connected through a termination component, as well as the distance through that termination component.
The PCB panel includes an xSignal mode that is used to examine and manage the xSignals. The panel also provides feedback on the signal length, highlighting xSignals that are close to meeting (yellow) or failing to meet (red) the applicable design constraints. In the image below the xSignal lengths of the CLK1 differential pair are different in length by more than allowed by the applicable Matched Length design rule. The panel includes the Signal Length, which is an accurate point-to-point length. Traditional length inconsistencies, such as tracks within pads and stacked track segments, are resolved, and accurate via span distances are used to calculate the Signal Length.
Main article: Controlled Impedance Routing
Traditionally, board designers would define the widths and thickness of the routing by entering a dimension for the width and selecting a thickness of copper for that layer. This was generally sufficient since you only needed to ensure that the current could be carried and the required voltage clearances were maintained. This approach is not sufficient for the high-speed signals in your design, for these you need to control the impedance of their routes.
Controlled Impedance routing is all about configuring the dimensions of the routes and the properties of the board materials to deliver a specific impedance. This is done by defining a suitable impedance profile, and then assigning that profile to the critical high-speed nets in the routing design rules.
Impedance profiles are defined in the PCB editor's Layer Stack Manager (Design » Layer Stack Manager). The Layer Stack Manager opens in a document editor, in the same way as a schematic sheet, the PCB, and other document types do.
Once the layer properties have been configured, switch to the Layer Stack Manager's Impedance tab to add or edit single or differential impedance profiles.
The routing impedance is determined by the width and height of the route, and the properties of the surrounding dielectric materials. Based on the material properties defined in the Layer Stack Manager, the required routing widths are calculated when each impedance profile is created. Depending on the material properties, the width may change as the routing layer is changed. This requirement to changes widths as you change routing layers is automatically managed by the applicable routing design rule configured in the PCB Rules and Constraints Editor (Design » Rules).
For most board designs, there will be a specific set of nets to be routed with a controlled impedance. A common approach is to create a net class or differential pair class that includes these nets, then create a routing rule that targets this class, as shown in the images below.
Normally you manually define the Min, Max and Preferred Widths, either in the upper constraint settings to apply them to all layers; or individually for each layer in the layer grid. For controlled impedance routing you enable the Use Impedance Profile option instead, then select the required Impedance Profile from the dropdown. When this is done, the Constraints region of the rule will change. The first thing you will notice is that the available layers region of the design rule will no longer show all signal layers in the board, it will now only show the layers enabled in the selected Impedance Profile. The Preferred Width values (and diff pair gap) will update to reflect the widths (and gaps) calculated for each layer. These Preferred values cannot be edited but the Min and Max values can, set these to suitable smaller/larger values.
For single-sided nets, the routing width is defined by the Routing Width design rule.
The routing of differential pairs is controlled by the Differential Pair Routing design rule.
► Learn more about Differential Pair Routing
So how do you know what target impedance to select? This is normally driven by the characteristic source impedance of the logic family or technology being used. For example, ECL logic has a 50Ω characteristic impedance, and TTL has a source impedance range of 70Ω to 100Ω. 50Ω to 60Ω is a common target impedance used in many designs, and for differential pairs, 90Ω or 100 Ω differential impedance is common. Remember, the lower the impedance the greater the current drain, the higher the impedance the more chance there will be EMI emitted, and the more susceptible that signal will be to crosstalk.
A 100Ω differential pair can also be viewed as two, 50Ω single-ended routes that have the same length. This is not exactly correct due to the coupling that occurs between the pair, which becomes stronger as they become closer, reducing the differential impedance of the pair. To maintain 100Ω differential impedance the width of each route can be reduced, which slightly increases the characteristic impedance of each route in the pair by a few ohms.
Main article: Layer Stack Management
The materials used for the layers in your board, their dimensions, and the number of and order that the layers are arranged, are all defined in the Layer Stack Manager. Here you configure the various layers that are needed to fabricate the final board including the copper signal and plane layers, the dielectric layers that separate the copper, the cover layers, and the component overlay.
Main article: Defining the Via Types
As mentioned in the overview section of this article, vias affect the impedance of the signal routing and are a key consideration in high-speed design. As well as the length, hole diameter, and via land area affecting the impedance that the signal sees, any unused portion of a via barrel can act as a stub, contributing to signal reflections. To manage this, various layer-to-layer via styles can be fabricated, including Blind, Buried, µVia, and Skip Vias. These via types are all supported in Altium Designer.
Vias are defined as part of the layer stack, in the Layer Stack Manager's Via Types tab. Back drilling of unused via barrels is also supported, these are defined in the Layer Stack Manager's Back Drills tab (Learn more about configuring the board for back drilling).
Quantitative studies have been performed to understand the impact of vias, such as the Altera Application Note AN529 Via Optimization Techniques for High-Speed Channel Designs.
Summarizing this study and other references, the following guidelines are given to help minimize the impact of vias:
A good quality return path is essential for each high-speed signal in the design. Whenever the return path deviates and does not flow under the signal route, a loop is created and this loop results in EMI being generated, with the amount being directly related to the area of the loop.
A good quality return path is one where:
There is general agreement that a ground plane should not be split unless there is a specific requirement for it and you understand how to define and manage it. Instead, the components should be arranged to keep noisy components separate from quiet components, and to also cluster components by the supply rail that they use.
Other points to keep in mind about power and ground planes include:
To help with the task of visually checking the return paths, you can configure the display so you can more easily examine the return path under the critical route paths.
To do this:
Your net(s) will stand out, and any splits or discontinuities that lie in the return path, such as split lines or blowouts created by through-hole pads and vias, will be easier to see.
Breaks or necks in the return path can be detected by the Return Path design rule. The Return Path design rule checks for a continuous signal return path on the designated reference layer(s) above or below the signal(s) targeted by the rule. The return path can be created from fills, regions, and polygon pours placed on the reference signal layer, or it can be a plane layer.
The return path layers are the reference layers defined in the Impedance Profile selected in the Return Path design rule. These layers are checked to ensure the specified Minimum Gap (width beyond the signal edge) exists along the signal's path. Add a new Return Path design rule in the High Speed rule category.
The image below shows return path errors detected for the signal,
NetX, with a Minimum Gap setting of
0.1mm. It can be easier to locate Return Path errors by configuring the DRC Violation Display Style to show Violation Details but not the Violation Overlay ( show image), in the Preferences dialog. Doing this highlights the exact locations where the rule has failed, rather than the entire object(s) in violation.
The definition of differential pairs can be done during schematic capture, or they can be defined once the design has been transferred to board layout. A core requirement of defining a pair on the schematic is to include an
_N at the end of the Net name for each of the relevant nets. Differential pairs are identified on the schematic by placing a Differential Pair directive on each net, or by placing one on a Blanket directive, where the Blanket directive overlays a set of enclosed differential-style Net Labels, as shown in the image below.
Working with Differential Pairs:
_Npad to commence routing, then use the Spacebar to cycle through the available exit routing shapes. The routing behavior is the same as single net routing, press Shift+F1 for a list of interactive routing shortcuts. As you approach the target pads, press Ctrl+Click to complete the routing up to the pads.
Differential Pair rules of thumb:
A key requirement of managing high-speed signals on a board is to control and tune their route lengths.
The delay caused by the length of the pin within the device package is supported, to learn more read about Pin Package Delay.
Nets that include serial components in their path are managed by defining xSignals.
To understand how the settings of these two rules are resolved when both are present in a design, refer to the Length Tuning page.
Current route lengths are displayed in the Nets mode of the PCB panel, and are updated as you route. The Routed length value will go yellow as you approach the target length, and turn red if you exceed it.
If there is a Length rule and/or a Matched Length rule defined, you can monitor the length during interactive routing or length tuning by displaying the Length Tuning Gauge. While you are routing, use the Shift+G shortcut to toggle the Gauge on and off.
The Gauge shows the current Routed Length as a number over the top of the slider, while the slider shows the Estimated Length. During length tuning the
Estimated Length = Current Routed Length; if you are using the Gauge during interactive routing then the
Estimated Length = Routed Length + distance to target (length of connection line).
MinLimit) is 46.58
MaxLimit) is 47.58 (obscured by the green bar in the image above)
TargetLength) is 47.58 (route length of the longest net in the set, equal to
Route lengths can be tuned after the routing is complete, using the Interactive Length Tuning command, or the Interactive Diff Pair Length Tuning command (Route menu). These commands add accordion sections to the routing, in a choice of three shapes.
If there is an applicable Length rule and Matched Length rule, the length tuning tool considers both of these rules and works out the tightest set of constraints. So if the maximum length specified by the Length rule is shorter than the longest length targeted by the Match Length rule, then the Length rule wins and its length is used during tuning.
To see which rules are being applied or to change the accordion properties during length tuning, press Tab to open the Interactive Length Tuning mode of the Properties panel, as shown below. Note the Target Length, this is the Max Limit of the strictest applicable rule settings.
To tune the length of a net, run the command and then click anywhere along the net's length. Move the cursor so that it follows the path of the route, tuning accordion sections will be added as you do. Tuning sections will continue to be added until the length requirements defined by the applicable design rule(s) have been satisfied. If the cursor moves outside the bounds of the tuning accordions, the accordion shapes will disappear - when the cursor is moved so that it is back within the bounds of the accordion shape, they will re-appear.
► Learn more about Length Tuning
While it is not possible to derive a universal set of rules that apply to every high-speed design, it is possible to follow good design practices that will help you succeed with your high-speed design. There are a number of industry experts that deliver practical and popular training courses on high-speed design. Use the links below to learn more, and to research specialized training options.
The author gratefully acknowledges the work of the following industry experts, this article is an attempt to summarize their collective knowledge.
PCB Layout - Learn EMC website
Keith Armstrong articles, EMC Information Centre (free registration required)
The Electronic Packaging Handbook - Glenn R. Blackwell
The Printed Circuits Handbook - Clyde Coombs and Happy Holden
The HDI Handbook - Happy Holden and others
Via Optimization Techniques for High-Speed Channel Designs - Altera Application Note AN529
High-Speed PCB Design Considerations - Lattice Semiconductor Application Note TN 1033
Measuring a Signal's Flight Time - Chris Grachanen, EDN
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