Avoid adjacent layer parallel track routing

Created: 25.03.2021 | Updated: 12.08.2021

How to set a rule to avoid adjacent layer parallel track routing

Starting in Version: 18.0
Up to Version: Current

Solution Details

Use Altium Designer "Parallel Segment" high-speed design rule to avoid the adjacent layer parallel track routing.

Constraint.png
  • Layer Checking - specifies where the two track segments to be checked should reside:
    • Same Layer - the track segments for the targeted nets are both on the same layer
    • Adjacent Layers - the track segments for the targeted nets are on adjacent layers.
  • For a parallel gap of - specifies the parallel gap that should exist between two track segments before they can be considered for test.
  • The parallel limit is - specifies the maximum permissible parallel length of two track segments (on different nets), when the parallel gap constraint is observed over the entire length.
 
Here's documentation that covers the use of this constraint:
https://www.altium.com/documentation/altium-designer/pcb-dlg-parallelsegmentrule-frameparallel-segment-ad

 
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