BREAKING THE PCB DESIGN CHALLENGES WITH NET TIES
What is a Net Tie?
The Net Tie is a Component Type that allows PCB Engineers and Designers flexibility when Handling a Variety of Design Challenges. This Paper Explores the Advantages to using Net Ties in Altium Designer to Join Multiple Nets (shorts) Into One Single Net at Very specific Locations in the PCB.
Defining a Net Tie component is simply a matter of specifying it in the Type field of the Component Properties dialog.
Figure 1: Net Tie Component Properties Dialog
There are two types of Net Ties, Net Tie and Net Tie (In BOM). Each type is available on the pulldown options for Type in the Component Properties dialog. When using a Net Tie, the component schematic symbol graphic is attached to a specific type of footprint containing copper features connecting (shorting) the pads together. Net connectivity between the schematic symbol pins and printed circuit board PCB footprint pads is established in the customary way; however, no line item will appear for this component in the Bill Of Materials (BOM). Using the Net Tie (In BOM) allows materials to be called out in the BOM. Both types will be explored in this paper.
The simplest form of a net tie is a two pin component associated with a two pad footprint in which the pads are connected together with copper features.
As with other schematic symbol types, the display of symbol pin designators and display names are optional, schematic wiring between pins determines net connectivity, and there is a pin-to-pad connectivity established between the schematic and printed circuit board PCB. The graphic for a Net Tie component is arbitrary and in some cases unnecessary. For instance, a two pin Net Tie component may be represented to look like a piece of wire in a schematic sheet (totally hiding its existence).
Figure 2: Pin Net Tie Schematic Symbols.
Figure 3: A Net Tie footprint Possibly Used To Short Two Polygons Of Differing Net Names.
Together. This Component Would Call Out The Header Part In The BOM. The Shorting Copper May Be Removed At A Later Date To Allow The Application Of An Optional Shorting Jumper.
Figure 4: Net Tie (In BOM) Used To Designate A Two Pin Header With The Pins Initially Shorted
While routing to the pads of a Net Tie footprint, the Design Rule Checking (DRC) allows routing the nets associated with each pad to other same net copper features without flagging a violation, allowing the connecting (shorting) copper feature of the footprint to connect the two differing nets.
Track Of Two Different Nets
If the two track ends from differing nets short together across the footprint, the DRC will flag a violation. This is due to the short circuit being generated between two differing nets outside the constraints of the Net Tie footprint.
Track Of Two Different Nets Associated with a violation flagging
Figure 5: Net Ties with various Track Widths Net Ties can be Set Up to allow Routing two differing Nets together with Various Track Widths.
Figure 6: Net Tie components can be created to allow routing between various routing layers by incorporating through hole (Multilayer) pads.
This Allow The designer options for component placement at a later time. In this example, the short may be replaced with a surface mount resistor or inductor
Figure 7: Net Tie footprints can be created to allow shorting between nets, and later the shorting copper may be removed to allow components to be placed between nets. In this example, there is an 0805 and a 0602 footprint placed on top of each other with a shorting copper feature placed between them. This will allow the designer options for component placement at a later time. In this example, the short may be replaced with a surface mount resistor or inductor.
Net Tie components allow establishing a connection between two differing nets at and only at the location of the of the Net Tie footprint on the PCB. The DRC will flag any other short circuit violation between these differing nets elsewhere in the design.
Planar inductors pose a special challenge. When various windings of the inductor are placed directly on the PCB, each winding is composed of routing tracks creating the various inductor coils. Each coil is a continuous copper track with differing nets at each end of the winding.
The inductor winding track typically introduces a short circuit between each of the nets on the ends of the winding resulting in a DRC violation.
You can use Altium Designer to place a Net Tie component in series with the inductor windings. This provides a means of connecting differing nets, one net representing the winding and one side of the electrical circuit and the other net being the second electrical connection.
Figure 8 Circuit bridging
Figure 8: A circuit bridging two differing ground plane nets with a planar inductor winding. The Net Tie component provides a means of tying AGND to the EGND net, which is extant throughout the planar winding.
In this example, silkscreen and reference designators have been shown to illustrate the placement of the components; however, these features may be left off the actual design to elevate clutter and confusion in a high-density design.
Silkscreen and Reference Designators have been shown to illustrate the Placement of the Components
Here nets NT5, NT6, NT7, NT8, and NT 11 have been placed in a Component Class labeled NetTieDirect.
Polygons and Net Tie components
Figure 9: Net Tie components may be used to connect polygons of differing nets to allow shorting at one and only one place. Other short circuits between these two nets will be flagged as violations by the DRC.
Design Rules and Polygons
Figure 10: In the above example, multiple Net Tie components have been placed on a PCB to illustrate how design rules can be scoped to specify polygon connect style in order to achieve the desired result.
Figure 11:Two Polygon Connect style rules have been created for the example NetTieDirect and NetTieRelief, which are scoped to the Component Classes NetTieDirect and NetTieRelief respectively.
Example of NetTieDirect and NetTieRelief
Figure 12: In the upper area of the PCB, the Net Ties are connected to the polygons following the Relief connect rule.
Note that NT1 has a polygon connect on the left side and the DRC allows routing from the right pad to the polygon.
Figure 13 Examples of multi-pin Net Tie schematic symbols.
Figure 14: Extreme example of what can be achieved with Net Tie footprints.
The lower portion of the PCB follows the direct connect style. Notice how the polygon pulls back from the connecting (shorting) copper feature according to the clearance rules.
Net Ties may have an unlimited number of pins and pads electrically connecting an unlimited number of nets.
Net length tuning provides an interesting challenge when the signal path of time critical signals must arrive at the load end of the net at the same time within a reasonable delta. In the example below, the clock signal is generated and routed to two different IC packages. It is critical that the signal path of this high-speed signal have achieve the same length within a reasonable tolerance.
The Clock Signal is Generated and routed to two different IC
The use of a multi-net Net Tie allows the net to be broken out into separate nets for the purpose of length tuning. The associated footprint allows the same signal to travel different net paths
The nets CK1 and CK2 are associated into a Net Class labeled CLK and a Length rule is then created for this class.
Once the nets CK1 and CK2 have been routed they can be length tuned to the Length rule which specifies the total length and tolerance.
The associated footprint allows the same signal to travel different net paths
The nets CK1 and CK2 are associated
CK1 and CK2 have been routed they can be length tuned to the Length rule
The Net Tie is a unique component type that allows the engineer and PCB designer the flexibility to short different nets together. Following the steps above while using Altium Designer can help you address requirement challenges when designing PCB boards.