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Intelligent placement of PCB layers nullifies RF energy and results in PCAs that pass EMC on their first pass.
TOPICS IN THIS SOLUTION
Professional PCB design tool with proficient PCB layer stackup management.
Use inner layers with adjacent ground planes for clocks
When considering how to determine PCB layers stackup, the best practices is to prioritize signal integrity. Signal integrity occurs when RF current generation is avoided with careful organization of the layers. RF currents are generated through unwanted impedances built in the material giving opportunity to generate common-mode currents. Common-mode currents are the primary source of RF energy. RF energy gets into the power distribution network or emits into free space as noise. Noise presents itself as reflections, ringing, or crosstalk.
The PCB layer stackup may be designed to incorporate features useful to maintaining signal integrity. Maximum capacitive decoupling in the power distribution network is achieved by placing power planes directly adjacent to ground planes in the layer stackup (see figure above). Signal planes should always have a ground plane adjacent in the PCB stackup. Including a ground plane next to each signal plane enhances flux cancellation and removes noise. Minimizing spacing between conductive layers increases flux cancellation.
Intentional routing continues best practice layer stackup design for signal integrity. High-speed traces are best routed stripline to take maximum advantage of both shielding and of flux cancellation on the inner layers with adjacent ground planes. Less sensitive traces at low risk for coupling through air are best routed microstrip on the outer layers of the Printed Circuit Board. Further routing techniques incorporate aspect ratio for chassis ties with ground stitches between each. Ground fill between traces on outer layers with plenty of ground stitches provide return paths and mitigate creation of loop currents.
The root cause of noise in a PCB is development of RF energy across unwanted impedances throughout the PCB stackup. RF currents develop when unwanted impedances build within the Printed Circuit Board during design. Impedance builds as inductance on windings of inductors and on the leads of discretes such as resistors. Loops give opportunity for switching currents to produce RF energy into the air.
Whether it’s a single standard PCB thickness board, multiple boards, multilayer PCB, or a design where your primary concerns are the PCB traces, holes, and pads involved, impedance can always be an issue. ICs and interfaces with other materials cause mismatches that build unwanted impedance also leading to generation of RF currents. When unwanted impedance builds onto nets greater than that of air, RF energy takes the path of least resistance and emits into free space.
Finetune signal characteristics per layer during route
Mitigate RF energy with a floorplan that discourages unwanted impedances and unnecessary materials such as excessive copper weight thickness. Design the PCB stackup layers to eliminate impedance buildup and shunt RF energy to chassis. Route signals to ensure the return path is directly underneath the signal trace. Avoid making loops that generate impedance when fast-switching signals are present on a PCB. Evaluate Printed Circuit Board layers as buried vias are placed to ensure no discontinuities exist. Discontinuities produce slots in layer planes and can force return paths into loops that emit noise. Place decoupling capacitors on each component’s power rails to shunt switching signals to ground. Place bypass capacitors on switching signals at connectors entering and leaving the design.
Arrange power and ground layers adjacent to one another for clean power distribution throughout the PCB layers. Clean power distribution results from low impedance capacitive decoupling when power and ground layers adjoin each other in the stack. Continue design integrity for the power distribution network throughout the layers by adding decoupling capacitors at each and every component power lead interfacing to the PCB layers.
Designing around decoupling capacitors at each component power lead will provide energy for large digital networks that switch simultaneously. Proceed with power distribution integrity throughout the layers by adding decoupling capacitors at signal pins that undergo transitions during clocking. Decoupling and bypass capacitors provide enough energy to hold up intended signals during operation, preventing ground bounce and unintended injection of RF energy into the Printed Circuit Board layers.
Adjust critical impedances for high-speed signals
Layer signal planes adjacent to ground planes to prevent loops that generate RF energy. Loops cannot develop when return planes are located directly next to signal planes. Via placement is critical to avoid slots in the layer stack where signals may need to travel around slots thereby generating loops. In addition, high-speed signals develop flux in both the signal net and the return net.
This flux is equal and opposite, signal and return. Maximum cancellation occurs when high-speed signal and return are placed directly adjacent to one another. Cancellation of flux generated by high-speed signals must be accomplished to maintain electromagnetic compliance (EMC). Designing the layer stack to ensure return layers are adjacent to each and every signal layer results in electromagnetic compliance (EMC). EMC indicates the layer stack was designed to properly mitigate flux generation.
The Layer Stack Manager provides an elegant tool for PCB design guidelines and setting layer characteristics such as thickness. It is a visual tool set up as a table with direct access for Printed Circuit Board editing. Columns for material definition of copper, prepreg, and core along with surface materials are specified here. Realization of high-speed design requirements that employ designed thicknesses are inserted here along with definition of dielectric material.
Dielectric material for most Printed Circuit Boards today is FR4 and the Layer Stack Manager automatically inserts its dielectric constant into the stack manager. You may work in either Imperial or metric dimension units. Preset layer configurations are available to speed up your design work or you may load a previously configured stack from another design project. Drill pairs are accessible via a given navigation button. A separate radio button navigates to the Impedance Formula Editor.
Use the Impedance Formula Editor to control impedance for high-speed signals
Use built-in equations for calculating microstrip and stripline impedance for high-speed signals in your layers. The built-in equations are located in the Impedance Formula Editor within the Layer Stack Manager. The built-in equations pull from material thickness and dielectric of nonconductive laminates and from copper characteristics given in the Layer Stack Manager. Radio boxes within the editor allow direct access to equation variables should your design require analysis for embedded microstrip or dual stripline.
A printed circuit board is only as strong as its design, make sure that your software can get a board or boards out quickly and reliably through Gerber files accurately displaying PCB trace thickness, components, pads, and solder for heat dissipation. Don’t let your design suffer from board layouts that are inaccurate or have not been integrated properly between schematic board design and board layout.
Altium Designer is a powerful tool that gives you the Layer Stack Manager to set up PCB layers for RF energy nullification. If you’re looking into how to determine PCB layers, use the Layer Stack Manager to minimize stray impedance buildup using the Impedance Formula Editor. Use the Editor to carefully design high-speed signals to eliminate unwanted impedances that develop RF energy. Altium Designer tools intelligently set PCB layers and signal impedance so your PCA will pass EMC the first time.