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Retired Documentation No Longer Applicable to a Later Version of Altium Designer
Retired Documentation - Design Rules
Working with the Parallel Segment Design Rule on a PCB in Altium Designer
Created: 三月 23, 2017 | Updated: 八月 11, 2021
| Applies to versions: 18.0, 18.1, 19.0, 19.1, 20.0, 20.1 and 20.2
您正在阅读的是 19.0. 版本。关于最新版本，请前往 Working with the Parallel Segment Design Rule on a PCB in Altium Designer 阅读 21 版本
Rule category: High Speed
Rule classification: Binary
Summary
This rule specifies the distance two track segments can run in parallel, for a given separation.
Constraints
Default constraints for the Parallel Segment rule.
- Layer Checking - specifies where the two track segments to be checked should reside:
- Same Layer - the track segments for the targeted nets are both on the same layer
- Adjacent Layers - the track segments for the targeted nets are on adjacent layers.
- For a parallel gap of - specifies the parallel gap that should exist between two track segments before they can be considered for test. Parallel track segments with a gap of this value or less will be tested.
- The parallel limit is - specifies the maximum permissible parallel length of two track segments (on different nets), when the parallel gap constraint is observed over the entire length.
How Duplicate Rule Contentions are Resolved
Duplicate rules do not create contentions for this rule.
Rule Application
Online DRC and Batch DRC.
Note
This rule detects parallel track segments that are within the parallel gap setting, then adds all segment lengths that are in those nets. When the sum of these segment lengths exceeds the parallel limit, a DRC violation is flagged. A simple example is shown below.
