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Working with the Hole To Hole Clearance Design Rule on a PCB in Altium Designer

Created: 三月 23, 2017 | Updated: 九月 26, 2019 | Applies to versions: 18.0, 18.1, 19.0, 19.1, 20.0, 20.1 and 20.2
您正在阅读的是 20.0. 版本。关于最新版本，请前往 Working with the Hole To Hole Clearance Design Rule on a PCB in Altium Designer 阅读 21 版本
 

Rule category: Manufacturing

Rule classification: Binary

Summary

This rule ensures checking of manufacturing compatibility of drilled holes. When enabled, it will flag any multiple vias / pads at the same location, or overlapping pad / via holes. There is also an option to determine whether stacked micro vias are allowed or not.

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.

Constraints

Default constraints for the Hole To Hole Clearance rule.Default constraints for the Hole To Hole Clearance rule.

  • Allow Stacked Micro Vias - enable this option to allow micro vias to be stacked. 
There are many advantages of using micro vias:
  • Such a via requires a much smaller pad, which helps to reduce the board size and weight.
  • They allow IC components to be more densely placed. This could result in the use of a smaller PCB, which would bring a welcome reduction in total board manufacturing costs.
  • They facilitate improved electrical performance, due to shorter pathways.
  • Hole To Hole Clearance - the value for the minimum permissible clearance between pad/via holes in the design.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expressions match the object(s) being checked.

Rule Application

Online DRC and Batch DRC.

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