Clearance Constrain between polyregion on multilayer and pad on top layer

Created: March 25, 2021 | Updated: August 12, 2021

I have an error stating "Clearance Constrain between polyregion on multilayer and pad on top layer" on my PCB layout. Every pad is having this error, as well as a through hole component. When I click to "jump to" the violation... It goes to the corner of the board and just says there is a clearance violation.

Starting in Version: 18.0
Up to Version: Current

Solution Details

This error usually occurs when you do not have any stackup assigned to the board. You can go to board planning mode (by pressing the "1" key), then right-click on a board region to choose Properties from the context menu which will bring up the Board Region dialog so that you can assign the stack up to the board region. 


Here's documentation with a little more detail:
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