KB: Validate transmission impedance computed in layer stack
Altium Designer
[Why] Validate transmission impedance computated in layer stack, as the result is inconsistent with other third-party calculators/tools. [What] Under the hood, there is a fundamental difference between a web calculator based on formula of closed-form expression and the numerical computation done within Altium's Layer Stack Manager powered by Simbeor's 2D quasi-static field solver based on Method of Moment and validated by convergence, comparisons, and measurements. [How] Check for detail options such as 'Use Surface Finish' and 'Use Solder Mask' in Layer Stack Manager which could attribute to the difference from a web calculator result. Reference plane is also another parameter frequently overlooked. The bottom line, consult your board fabricator and stay with an oversized estimation for trace width/gap so you have a room to modify them later.
Solution Details
You can read more here:https://www.altium.com/documentation/altium-designer/interactively-routing-controlled-impedance-pcb#!the-simbeor-sfs
https://forum.live.altium.com/#/posts/249000/783549
Additionally, options such as 'Use Surface Finish' and 'Use Solder Mask' in Layer Stack Manager could attribute to the difference from a web calculator result, typically without such consideration.
Reference plane is also another parameter frequently overlooked, and if unspecified for Coplanar configuration, Altium assumes that it is on the same layer as the signal with S (clearance) being the only dependent parameter associated with adjacent conductors.
https://www.altium.com/documentation/altium-designer/interactively-routing-controlled-impedance-pcb#!support-for-coplanar-transmission-line-structures
If you also have no reference on each side of the routing then theoretically this is not coplanar i.e. "impedance controlled" it is just differential pair routing. Ultimately you could consider adjusting the spacing "S" to the ground shielding to a significantly large value. If you are making these type of adjustments you should consider any possible ramifications from those settings.
Here is another paper comparing web calculators and Simbeor SFS integrated in Layer Stack Manager since its inception in 2020:
https://resources.altium.com/sites/default/files/2020-03/Impedance%20Calculation_fin2.pdf
The bottom line, however, is that it is best that you consult your board fabricator upfront, and when in doubt, try to stay with an oversized estimation for trace width/gap, so that you have a room in your board later to narrow them after you solidify the spec with your fabricator. Here is another forum thread on the topic discussed among other expert users:
https://forum.live.altium.com/#/posts/251714/798646
It is also worth mentioning that there is a convenient command Retrace to update existing trace width/gap of an obsolete impedance profile in one go.