Advanced HDI Design Using Altium Designer
There are a number of new materials used in HDI that does not appear in the construction of conventional multilayer; RCC, RRCF, liquid and dry film dielectrics and spread-glass prepregs. This chapter will illustrate the use of Altium Designer 19 in creating these constructions.
TOPICS IN THIS SOLUTION
The defining characteristic of High-Density Interconnects (HDI) is the blind and buried via structures. In addition to the microvias, are the thin materials used in conjunction with blind vias as their aspect ratio is less than 1.0. As was illustrated in Chapter 2, there are a number of new materials used in HDI that does not appear in the construction of conventional multilayer; RCC, RRCF, liquid and dry film dielectrics and spread-glass prepregs. This chapter will illustrate the use of Altium Designer 19 in creating these constructions:
- Defining HDI stackups
- Distributed Capacitance
- Defining Microvia structures
- Staggered Blind Vias
- Skip blind Vias
- Stacked Blind vias
- Mechanically Drilled blind Vias
- BGA Breakout
- Channels and Boulevards
- Routing on HDI Layer-Pairs
FIGURE 1 Ease of stackup definition in Altium Designer
Altium Designer comes with a few standard materials already in its library. You will have to add those HDI materials discussed in Chapter 2 of this Guidebook. This is easily done by accessing the Layer Stack Manager by choosing Tools>> Material Library from the main menus. These can then be used for an HDI stackup as seen in Figure 1.
A very special group of thin materials are those that create distributed capacitance for the Power Distribution Network (PDN). Many believe that there are only a few of these ‘buried capacitance’ materials but actually, the list is far larger, as shown in Table 1. That is because any dielectric of 0.000127 mm (0.005 in) or less between power and ground will create capacitances suitable to dampen any high-frequency noise on the PDN. Of course, the thinner the dielectric and higher the dielectric constant, the greater will be its effect, as shown in Table 1. These dielectrics are copper clad laminates (CCL), polyimide films (films), prepregs and resin coated foils (RCF).
TABLE 1 32 standard PCB dielectrics suitable to be used as a distributed PDN dielectric; CCL, polyimide film, prepregs and RCF.
Altium has made using microvias very easy. The difficulty is selecting the right microvia (HDI) structure. These various constructions are shown in Figure 2. They are also defined by the IPC in the HDI Design Standard, IPC-2226. As Type I to Type VII. All of these can be used in Altium Designer, as illustrated in Figure 3.
FIGURE 2 Three different microvia (HDI) structures: a. Staggered microvias with buried via; b. Stacked microvias offset from the buried via; c. All stacked vias, also called ELIC, popular in mobile phones for its density.
FIGURE 3 HDI via definition screen where various HDI vias are assigned layers. The property screen defines various diameters.
The screens in Altium are not scaled for dimensions, but for constructions, Layer Stack Visualizationcan provide that.
Staggered Blind Vias
Staggered microvias on a single side or both sides with just through-holes is the most common and lowest cost HDI structure. The various microvia structures from Altium are shown in Figure 4, including staggered, skip, and buried. HDI via default to be centered, but after placement can be moved to be adjacent or inset (as seen in Figures 8 & 10 of Chapter 4).
FIGURE 4 Staggered via travers only one layer at a time
Figure 5 shows the crankshaft type of staggered vias from the IPC-2226 HDI Design Standard. The distance between staggered microvias can be varied from inset to adjacent to a full dogbone style.
When using multiple staggered microvias to connect inner-layers, it is preferred that the microvias rotate, as in a crankshaft, in order to minimize the vias effect during any thermal excursions. As these vias expand when heated, they will influence other vias in their vicinity, (seen in Figure 6). Be sure to contact your PCB fabricator for material and process compatibility if multiple HDI build-up construction is anticipated.
FIGURE 5 Staggered via ‘crank-shaft’ style construction.
FIGURE 6 Multiple build-up HDI layers connecting to a buried via.
Skip Blind Vias
The skip microvia is special in that it is used to ‘skip’ the next adjacent layer, as seen in Figure 7. Because the skip microvia can be the deepest of microvias, it is important that the designer be aware of a fabricator’s capability to produce and metallize such a microvia. Many will not have this capability, so it is wise to check before designing with one. And with all blind vias, the aspect ratio may be reduced to 0.70:1.0 or even 0.65:1.0, so the surface pad and target pad will be larger.
FIGURE 7 Skip microvia can go between two dielectrics (i.e. Layer_1 to Layer_3) and are used when another full build-up layer is not needed.
Stacked microvias use the least amount of board real-estate but are significantly more difficult to fabricate. This stems from the need for the target land of the top microvia having a solid metal surface to connect to. The process requires filling of the microvia either with conductive materials and plating it over (VIPPO) or with the use of “super-fill copper plating” capable of solid copper plating the microvia interior. This structure is seen in Figure 8.
Currently, it is recommended that stacked microvias not be stacked on a larger drilled buried via. Reliability concerns have arisen from this practice. Be sure to contact your PCB fabricator about this construction and read the IPC White Paper on “Performance-Based Printed Board OEM Acceptance-Via Chain Continuity Reflow Test: The Hidden Reliability Threat-Weak Microvia Interface-IPC-WP-023” of May 2018.
FIGURE 8 Stacked microvias require a solid metal surface for the ‘landing pad’ of the top microvia. The lower microvia needs to have its laser produced void to be filled and plated over.
Mechanically Drilled Blind Vias
So-called microvias can also be mechanically drilled from the surface. These are usually larger diameters than laser drilled microvias and can have special requirements for layer spacing, as the drill has a conical tip, can wobble, and are very fragile.
This also applies to sequentially laminated, thin 2-sided plated materials. This is seen in Figure 9 and can be utilized in Altium either as a Property (not a microvia) or with the Backdrilling property.
FIGURE 9 Mechanical drilled blind vias can be treated as “Backdrilling” or by not ‘checking’ the microvia box in Properties.
Fine-pitch BGA are fanout either by using the microvia within the pad or by using a microvia that is only touching the SMT pad . If routing with 0.1mm or 0.075mm traces, then via-to-via spacing is shown in Table 2. Figure 10 shows these possible breakout routing schemes for different fine-pitch BGAs.
Notice in Figure 10 that for 0.5 mm and 0.4 mm pitches the via holes are not in the center of the lands. This is to improve the spacing on the traces on the inner layers to a minimum of 0.075mm. The 0.5 mm pitch BGA with the 0.25 mm SMT land and 0.22 mm inner layer pad is illustrated. When selecting design rules for fine-pitch BGAs, be sure to contact your favorite PCB fabricator to find out what geometries he can support and tolerances that he can hold.
TABLE 2 Design rules for SMT BGA lands, blind vias, traces widths and spacings for fine-pitches of 0.65mm, 0.5mm and 0.4mm.
In addition to the traditional N-S-E-W dogbone breakout of BGAs, microvias, because of their much smaller size, allow two new methods of BGA breakout that greatly increases routing density and lowers layer count; Channels and Swing-via placement.
FIGURE 10, Illustrations of the Design rules for SMT BGA lands, blind vias, traces widths and spacings for fine-pitches of 0.65mm, 0.5mm and 0.4mm.
When a BGA’s total signal escapes begin to exceed 400 pins, it becomes advisable to place microvias, not on the peripheral for breakout, but as rows that cross the BGA as seen in Figure 10. These form ‘channels’ on the inner-layers and far side of the board that allow access to internal signals of the BGA and thus require fewer layers for total breakout.
The BGA in Figure 11 is a 1153 pin (34x34) BGA (1.0 mm pitch) and has 132 possible routes per layer (1 trace between vias) plus 20 traces in the channel (5 traces). This means that 8 layers would be required (plus 5 plane layers) to connect this BGA to the rest of the circuit.
If we create more routing channels, we connect more traces per layer and reduce the total layers. Channel Routing uses blind microvias to form up to 4 additional cross-shaped, L-shaped or diagonal channels in a BGA fanout pattern. The new channels allow up to 48 extra connections per layer (8x6 traces). Two routing layers and two plane layers can be eliminated.
The channels can be ‘cross-like’, ‘L-shaped’ or ‘diagonal’, depending on the BGAs layout of ground and power pins as shown in Figure 12.
FIGURE 11 Placement of microvias within a BGA to form channels for interior signals to escape.
FIGURE 12 Routing channels formed by microvias to make breakout of large BGAs easier can be cross-shaped, L-shaped or diagonal shaped.
Swing Break-Outs for Boulevards
A swing via is actually a pair of vias that are fanned out between two Component (Part) pads to optimize the available area for routing conductors between them. Instead of the single breakout via of the N-S-E-W dog-bones, the smaller microvias have room for two adjacent breakout vias, as shown in Figure 13.
The microvia pads are so much smaller than the TH pad that there is even room for a surface ground flood, down to a 0.65mm pith (Figure 13).
FIGURE 13 Example of ‘swing breakout’ for a large 0.8mm BGA that includes a surface ground fill.
To calculate the spacing and angle of the ‘swing-vias’, simple geometry is used based on the 6 dimensions:
- BGA Pitch
- BGA SMT land size
- Microvia pad size
- Minimum distance between breakout microvias
- Whether microvias are in a straight line, staggered or adjacent to BGA lands.(dist. To microvia)
- If skip microvias are used (L1-L3), normal microvias (L1-L2) or both
Selecting the X-distance and Y-distance, the arcTan will provide the microvia distance and the angle (0) for the placement of the microvias, as seen in Figure 14. Trig formulas are available from MS Excel.
To achieve higher routing density with HDI, if possible, assign your surface routing layers to be a X-Y layer pair. Also, it can be practical to move the reference ground plane to the surface as a GND Flood. The small HDI geometries plus plane keep-outs are smaller than a mechanical drill anti-pad on an inner-layer plane.
FIGURE 14 Simple trigonometry will allow you to calculate via spacing and swing angle.
Higher density is achieved if signals-horizontal are connected with signal-vertical by a small microvia, or skip microvia or small drilled via, as seen in Figure 15.
FIGURE 15 Three possible stackups that permit X-Y routing using microvias and not larger drilled vias as cross-over.
For high-speed signal, the return path of a circuit is the path of least inductance, thus it follows the outgoing signal back on the reference plane. The miniature nature of HDI and fine pitch, allows for the outermost GROUND plane to be brought to the surface and used as a GND FLOOD, as seen in Figure 13. Remember, to have the GND flood continuous for the return path or noise will be generated and if switching return planes to have a via available for the return currents.