Altium NEXUS Documentation

Working with the Flight Time - Rising Edge Design Rule on a PCB in Altium NEXUS

Created: March 18, 2022 | Updated: March 18, 2022
All Contents

Rule category: Signal Integrity

Rule classification: Unary

Summary

This rule specifies the maximum allowable flight time on signal rising edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes to drive the signal on the net to the threshold voltage (marking the transition from signal LOW to signal HIGH), less the time it would take to drive a reference load (connected directly to the output) to the threshold voltage.

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.

Constraints

Default constraints for the Flight Time - Rising Edge rule.Default constraints for the Flight Time - Rising Edge rule.

  • Maximum (seconds) - the value for the maximum permissible flight time on the rising edge of the signal.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application

Batch DRC and during Signal Integrity analysis.

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