External and Schematic Net Names are Unsynchronized

Parent category: Violations Associated with Nets

Default report mode: 

Summary

This violation occurs when a Net Name of a pin of a schematic FPGA component does not match the external source file Net Name of a pin.

Notification

If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the Preferences dialog) an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:

External  <NetLabelName> and Schematic <NetLabelName> are Unsynchronized for Pin <xx>

where:

• NetLabelName is the name of the offending net label.
• xx is the pin number.

Recommendation for Resolution

In the Pin Mapper dialog with the offending Pin selected, in the Schematic region, access the drop-down solution options then choose Update Pin File () to transfer the net name from the schematic to the external FPGA pin file then recompile the project.