Project Compiler Violations Reference_AD

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The process of compiling is integral to producing a valid netlist for a project. In fact it is the process of compilation that yields the unified data model of a design - the single model of the data that is accessible across the design domains in Altium Designer's unified design environment. Connectivity awareness in your schematic diagram can be verified during compilation according to rules defined as part of the options for the design project - on the Error Reporting and Connection Matrix tabs respectively.

This area of the Altium Designer documentation provides a comprehensive reference describing each of the possible electrical and drafting violations that can exist in source documents when compiling a project.

For a detailed overview of verifying your captured design, see Compiling and Verifying the Design.

Violations are grouped into the following categories:

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软件的功能取决于您购买的Altium产品级别。您可以比较Altium Designer软件订阅的各个级别中包含的功能,以及通过Altium 365平台提供的应用程序所能实现的功能。