As specified ‘no go’ areas during design layout, Keepout objects use the existing Clearance Constraint Rules to control routing and detect placement violations, but unlike other placed objects, cannot be assigned to a Net and are not shown in generated Outputs or printouts. In its simplest sense, a Keepout acts as an ‘interference’ object that prevents other copper objects from intersecting its area, as specified by the global Clearance Rule.
Altium Designer allows for the creation and application of Keepouts with its support for Object Specific Keepouts. Placed Keepout objects can be configured to specify which type objects they apply to, such as tracks, copper areas, vias, and pads, which significantly enhances the flexibility and effectiveness of Keepouts.
In the PCB and PCB Library Editor, objects assigned as Keepouts are indicated by the current Restricted for Layer color. Keepout objects set to a specific signal layer are outlined by the Keep-Out color, whereas Keepouts set to the Top or Bottom layer display with cross-hatching and appear on the Keep-Out Layer itself.
Keepouts are ideal for defining non-routable board regions (such as electrically sensitive or high voltage areas), specifically exposed copper locations such as in Fiducials and Test Points, or mechanically incompatible areas (such as mounting holes or the corners of a PCB). The configurable nature of Object Specific Keepouts also allows them to be placed over other objects when specific Keepout Restrictions have been assigned. When set to restrict only Vias, for example, a Keepout can be placed over existing copper regions (such as a Polygon Pour) to control the extent of automated Via Stitching.
Object Specific Keepouts can be placed in the PCB Editor and PCB Library Editor.
A Keepout is placed in the editor workspace from the Place » Keepout menu, where the nominated Keepout style (Track, Fill, Region, or Arc) will be placed on the currently active Layer. Select the Keepout’s Properties to edit its physical characteristics, layer or object type restrictions. The related Keepout properties are:
In the below image, the two Keepout Fills have different Layer and object restrictions applied. These allow the Top Layer Keepout Fill (on the left) to accept a Through Hole (TH) Pad while restricting all other object types, and the Bottom Layer (right) to accept tracks only.
The inherent flexibility of Keepouts allows their use for a wide range of tasks to control PCB layouts. Since Keepouts can be overlaid, assigned to any signal layer (such as Top or Bottom), and configured to reject specific objects, they can be used to tightly control Via Stitching and Polygon Pours, for example.
In the example PCB layout shown below, Keepout Fills have been added around the multilayer Pads in a region of potential high voltage, which needs to have sufficient electrical isolation from the pending ground-connected Polygon Pours. The Keepout Fills are set to Top Layer and configured to restrict only Copper objects, which will reject Polygon Pours, Fills and Regions while accepting existing tracks and pads, etc., – in other words, the Clearance violation Rule will only apply to objects classed as 'copper'.
The above arrangement of Keepouts will force Polygon Pours placed on the signal layers (in this case the Top and Bottom Layers) to avoid all three Keepout areas. However, the top layer pads associated with the area of concern will not be provided with adequate clearance by the Top Layer Pour.
In this case, further Keepouts can be added to the Top Layer so that its Polygon Pour will avoid all the related pads by a suitable distance. In the image shown below, another two Keepout Fills have been added to the Top Layer, which is displayed here in Single Layer mode for clarity. Note that the Keepout coverage shown could have been created from a single Region, rather than two overlapping Fills.
When the Polygon Pours are eventually added to the layout, the collection of Keepouts will control the pours to produce a different clearance shape for each layer around the region. Note that in this example, the clearance associated with Keepouts is greater than that for normal objects due to a custom Keepout Clearance Rule (see below).
The influence of the Keepout collection on the Polygon Pours can be seen clearly when the layout is viewed in Single Layer 3D mode, as shown below – Top Layer on the left and Bottom Layer on the right.
The application of Keepout shapes, configured to restrict Via objects, on multilayer copper areas can control the extent of automated Via Stitching (Tools » Via Stitching/Shielding). The Keepout shapes can be set for any layer or one of the copper area layers so that Vias between those layers will be ‘kept out’ (restricted).
In the example shown below, Keepout shapes have been added to the upper and lower left corners of the layout. These are configured to restrict Via objects, which will prevent the automated Via Stitching from placing Vias within those perimeters.
Along with avoiding existing Tracks, Pads and Vias, as is normally the case, the Via Stitching also avoids the Keepout shapes as determined by the applicable Clearance Rule.
Keepouts are added to component Footprints in the PCB Library Editor using the same approach as those applied within the PCB Editor workspace.
The Keepout added to the component Footprint shown below is configured to restrict all objects, but allow tracks – therefore enabling Net connections in a layout where the component is used, while restricting the close placement of other object types.
The implementation of Altium Designer’s Object Specific Keepouts is reflected in all associated functions, and includes compatibility with the Queries (and therefore Design Rules), the PCB List panel, and also imported/older PCB design documents.
As is the case for other object primitives, the current Electrical Clearance Rule will determine the clearance constraints for Keepouts – see Design » Rules. If a different clearance constraint is required for Keepouts, create a specific Rule by applying the
IsKeepOut Attribute Check as a Custom Query.
Ensure that the custom Keepout Clearance Rule is set to a higher priority than the existing (global) Clearance Rule. In the example below, a rule has been created for Keepouts (
Clearance_to_Keepouts) with double the clearance constraint distance of the base Clearance Rule (
Clearance). As shown in the section of board layout, the track routed between the two pads avoids the Keepout region (on the right) by a larger margin than the Top Layer region (left).
Existing Primitive objects on signal layers can be converted to Keepouts, on the same layer, using the Convert Primitives to Keepouts command (Tools » Convert » Convert Selected Primitives to Keepout).
The PCB Filter panel allows the use of the
IsKeepOut Query word to locate and (optionally) select Keepouts objects in the design.
The PCB List panel can be used to list, select and edit the Keepout object of the selected type – for example, Keepout Fills, as shown in the below List panel image. A standard Top Layer Fill (the last listed) is also shown for comparison. If all the Fills (or other types of objects, such as Regions) included in the design are assigned as Keepouts, then the PCB List panel will include the full set of Keepout object Restriction attributes.
Altium Designer is able to import design files from a wide range of other design tools using the automated conversion capabilities provided by the Import Wizard (File » Import Wizard). Keepout type objects that are included in PCB design files from other design tools, some of which are object-specific, are converted to Object Specific Keepouts by the Wizard, where possible.
The Wizard’s Keepout conversion process is compatible with board designs from popular ECAD systems such as Mentor® Graphics Pads™ and Cadence® Allegro™. Correct Keepout interpretation also occurs during the IDF export process.
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