Project Compiler Violations Reference

Now reading version 15.1. For the latest, read: Project Compiler Violations Reference for version 21
Applies to Altium Designer versions: 15.1, 16.0, 16.1, 17.0 and 17.1

The process of compiling is integral to producing a valid netlist for a project. In fact it is the process of compilation that yields the unified data model of a design - the single model of the data that is accessible across the design domains in Altium Designer's unified design environment. Connectivity awareness in your schematic diagram can be verified during compilation according to rules defined as part of the options for the design project - on the Error Reporting and Connection Matrix tabs respectively.

This area of the Altium Designer documentation provides a comprehensive reference describing each of the possible electrical and drafting violations that can exist in source documents when compiling a project.

For a detailed overview of verifying your captured design, see Compiling and Verifying the Design.

Violations are grouped into the following categories:

Note

The features available depend on your level of Altium Designer Software Subscription.