Default report mode:
This violation is related to components and occurs when you have specified one or more pins to be hidden and connected to an existing net within the design – typically a power pin connected to VCC or GND for example.
If validation errors and warnings are enabled for display on the schematic (enabled on the Schematic – Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:
Adding items to hidden net <NetName>
NetName is the name of the target net.
Recommendation for Resolution
The problem arises when the following property for the offending pin(s) is evident in the associated Component Pin Editor dialog:
- The Show option is disabled.
The resolution of this issue is on a per-component basis and also depends on whether a component contains multiple sub-parts.
For a non-multi-part component, enable the display of the pin(s) in the design space (enable the Show option). You will need to wire each pin to the appropriate power port for the net to which you want to connect.
The previous solution can also be applied to multi-part components, but a far better solution is to set the Part Number field to
0. Leave the Show option for the pin disabled. Repeat for each pin that has been connected to a power net in this way. Ideally, the power net connections should be assigned through use of part
0 in the source library component.
Use the controls associated with the Object Hints entry in the Connectivity Insight Options region (the System – Design Insight page of the Preferences dialog) to determine the launch style for object hints (Mouse Hover and/or Alt+Double Click).