Altium Designer Documentation

WorkspaceManager_Err-DuplicateNetsDuplicate Nets_AD

Created: August 7, 2017 | Updated: February 28, 2019

Parent category: Violations Associated with Nets

Default report mode: 

Summary

This violation occurs when two nets with the same name have been detected within the design.

Notification

If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the Preferences dialog) an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:

Duplicate Net Names <Object> <NetName>

where:

  • Object is either Wire or Bus Slice or Element[n] (for a bus element)
  • NetName is the name of the affected net.

Recommendation for Resolution

When the design is compiled, nets are created in the following way:

  • Within each sheet, a unique net is created for each set of connected electrical objects.
  • The compiler then checks the Net Identifier Scope to determine if the design is flat or hierarchical.
  • If the design is flat, the sheet-level nets are connected directly between the various sheets.
  • If the design is hierarchical:
    • using the Port attached to the lower-level net, the connectivity is created from that Port up to the Sheet Entry in the Sheet Symbol on the parent sheet, then
    • the connectivity is created between the Sheet Entry and other connected electrical object on the parent sheet.

To learn more about flat and hierarchical designs, refer to the Creating Connectivity article.

This violation can arise when, for example:

  • The design is flat and ports have been used within the design. The Net Identifier Scope is automatically (or manually) set to Flat (Only ports global). The violation will occur if the same net label has been used between sheets. This is because net labels defined on each sheet, even with the same name, remain local to those sheets. The resolution in this case is to ensure unique net labeling is used between sheets.
  • The net continuity between flattened schematic sheets is broken by the inadvertent use of ports or offsheet connectors with different names. Use the Details region of the Messages panel to quickly cross probe to the duplicate net naming. Trace the net back to the incoming/outgoing port on each sheet and ensure the names for the ports are made the same.
  • You may have the same net used in two different branches of a hierarchical design - i.e. different sheet symbols are used to reference different child sheets, but the same name is used for the top-level sheet entries and descendent ports, and the two symbols are connected by a physical wire or bus. The net continuity between these branches can be broken by the inadvertent use of sheet entries with different names or the omission of a physical bus/wire connecting the sheet entries. Ensure that the physical wire connecting the two sheet symbols is in place and wired correctly and that the sheet entries are named the same.

Tip

  • Object hints will only appear provided the Enable Connectivity Insight option is enabled on the System - Design Insight page of the Preferences dialog. Use the controls associated with the Object Hints entry in the Connectivity Insight Options region of the page to determine the launch style for such hints (Mouse Hover and/or Alt+Double Click). 

 

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