Layer Stack Manager Enhancements (New Feature Summary)

Created: October 1, 2019 | Updated: August 26, 2021
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This release sees a number of new and improved features for the design of high-speed boards, including: the new return path design rule; delay-based net length analysis; support for snake routing; and a new interactive net length tuning engine.

Another element in the high-speed design toolkit is the impedance calculator built into the Layer Stack Manager.

This release sees improvements in the accuracy and the types of structures supported for impedance calculations, including:

  • New coplanar transmission line structures: single and differential coplanar structures are now supported by the Simbeor impedance calculator.
  • Greater control over the dimensional properties of the physical structure: support has been added for user-defined etched trace widths; the ability to define the soldermask thickness over the traces; as well as support for adjacent dielectric layers with different relative permittivity.
  • Modeling of Conductor Surface Roughness:  the higher the signal switching frequencies the greater the skin effect. Above 10 GB/s the roughness of the copper surface becomes a significant factor in conductor losses. Surface roughness can now be modeled and included in the impedance calculations.

New Coplanar Transmission Line Structures

The impedance calculator in the Layer Stack Manager now supports single and differential coplanar structures. Create a new impedance profile, then select Single-Coplanar or Differential-Coplanar from the Impedance Profile Type drop-down list.

Working with coplanar structures:

  • As with the standard single and differential impedances, values for each variable are automatically calculated based on the user-defined Target Impedance and Target Tolerance, and the physical properties of the board layers. These automatically calculated values can be adjusted by entering new values into the edit boxes of the Layer Stack Manager mode of the Properties panel.
  • To target the signal nets you want to be routed with a coplanar structure, configure a Routing Width (or Differential Pairs Routing) design rule with the Use Impedance Profile option enabled, and the required Coplanar Impedance Profile selected.
  • Coplanar structures require a reference plane on both sides of the signal route; this can be created by a polygon you place, or if stitching vias are added, by the Add Shielding to Net command (more info below). If you are placing a polygon, the separation between this polygon and the signal route is defined by the Clearance (S) value determined by Simbeor impedance calculator (displayed in the Properties panel, shown in the images above and below). Configure a Clearance design rule to control the clearance between the reference polygon and the signal route (show image).
  • It is common practice to include a via fence along each side of the signal trace when the coplanar structure is grounded, use the Tools » Via Stitching/Shielding » Add Shielding to Net command in the PCB editor to do this. As well as placing vias, by enabling the Add shielding copper option this command can also place a polygon around the signal routing to cover the via fence, as shown in the image on the right, below.
    Learn more about Via Shielding

The impedance calculator determines the signal properties and clearances (first image), use that clearance in the via shielding Distance setting.  The impedance calculator determines the signal properties and clearances (first image), use that clearance in the via shielding Distance setting.The impedance calculator determines the signal properties and clearances (first image), use that clearance in the via shielding Distance setting.

Conductor Surface Roughness

The surface of each of the copper layers in a printed circuit board has a degree of roughness. During PCB fabrication the surface of copper layers are treated to increase the roughness, to improve the adhesion between the copper and dielectric layers. This surface roughness becomes a significant contributor to conductor impedance at switching speeds above 10 GB/s. Through extensive research and analysis, industry experts have concluded that the surface roughness can be modeled by a roughness correction coefficient, derived from Surface Roughness and Roughness Factor values.

A Roughness region has been added to the Layer Stack Manager mode of the Properties panel. These parameters are used only for conductive layers.

Surface roughness is included in the calculation of the characteristic impedance.Surface roughness is included in the calculation of the characteristic impedance.


  • Model Type - preferred model for calculating the impact of surface roughness (refer to the articles below for more information on the various models). Applies to all copper layers in the substack).
  • Surface Roughness - value of the surface roughness (available from your fabricator). Enter a value ​between 0 to 10µm, default is 0.1µm
  • Roughness Factor - characterizes the expected maximal increase in conductor losses due to the roughness effect. Enter a value between 1 to 100, default is 2.

Further reading

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