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The practical performance of a PCB design layout depends on a multitude of factors, many of which can be predicted, to a reasonable degree, through a range of PCB design analysis tools such as post-layout Signal Integrity analysis. What's often neglected, however, or simply relegated to a 'rule of thumb' methodology, is developing the most effective layout design for board's DC Power Delivery systems. This is the judgment applied to the design of a board's copper areas that provide both the DC supply rails to the circuitry and their ground or common return path to the DC supply source. The desired outcome is an efficient design that maintains the integrity of the design's DC power layout.
With modern digital designs featuring high-speed circuitry, multiple devices, densely populated boards, and multiple supply rails, the demands placed on a design's DC power distribution network warrants a more analytical approach to its design. The DC analysis of a Power Delivery Network (PDN), or the results of its DC Power Integrity (PI-DC), is basically aimed at ensuring that adequate copper has been provided in the path from the voltage sources to the loads – in other words, that the planes, traces, and vias on the board are of sufficient size (and characteristics) to meet the power consumption requirements of the devices on the board.
Fortunately, the guesswork can be removed from the assessment of a PCB's power delivery network (PDN) through the use of a DC Power Integrity (PI-DC) simulation tool, which analyzes a board design's DC performance based on its electrical and physical properties. Such a tool is now available for Altium NEXUS as the Altium PDN Analyzer powered by CST® (Computer Simulation Technology).
Provided as a downloadable Altium Extension application, the PDN Analyzer integrates directly with Altium NEXUS to allow PI-DC simulation and analysis of the current PCB project. Since the PDN Analyzer functions within Altium NEXUS there are no manual data import/export requirements, data conversions or separate applications to be run – simply start the PDN Analyzer from the Schematic or PCB editor, set the desired test parameters and run the simulation. The results are primarily delivered through 2D/3D modeling of the circuit board copper layout, allowing a quick assessment of the results and the opportunity to perform exploratory 'what if' testing of the PCB layout design.
► See information on Installing and Licensing the PDN Analyzer extension.
First released as PDN Analyzer version 1.x, the significantly revised PDN Analyzer version 2.0 offers a redesigned interface, new features and more comprehensive results reporting.
The PDN Analyzer improvements include:
The following information on this page provides an overview of the basic electrical and practical principles that apply to Power Integrity Analysis and also includes installation and licensing information for PDN Analyzer v2.0.
► See the PDN Analyzer v2 Example Guide for information on performing power integrity simulations in PDN Analyzer v2.0.
In essence, the PI-DC (or 'IR drop') problem is fairly straightforward: the resistance embodied in the board's power supply shapes (traces, polygons, planes, etc.,) consumes power and voltage, robbing those from the various loads. As you would expect, the IR issues will increase in complexity with the number of loads on the supply through interaction in the power and ground copper paths.
Figure 1 (above) shows a simple block diagram of a circuit's power source and its power and ground shapes (traces and planes) that deliver power to the various loads (memory, microcontrollers, etc.). Note that all the loads are tied to the same power and ground shapes, and depend on those shapes to provide their operating voltage(s). In general, we tend to assume that those power and ground shapes have 0Ω resistance, which isn’t necessarily true, and that assumption can cause problems. Because relatively large currents are often involved, even small resistances in the power and ground shapes can cause significant power consumption (loss) and voltage drops.
Figure 2 demonstrates an example of the problems that can arise if the resistance of the power and ground shapes are not properly considered. Even though each shape has a relatively small resistance of only 0.25Ω, they have caused the voltage at the load to drop from 5V to 4.5V. The designer has to be aware of this drop and ensure it can be accommodated, or change the design to lessen it, to ensure that that the final design will not fail in the field.
The problem, however, seems easy to solve – simply make the power and ground shapes short or large enough to represent an insignificant resistance, using the following relationship:
R = ρ * L/A, where:
Ris the total resistance of a shape (trace or plane)
ρis the resistivity of the material used for the shape (typically copper,
ρ ≈ 1.7µΩ-cm)
Lis the length of the shape
Ais the cross-section area of the shape (width
Put simply, if you make your power and ground shapes short, thick and wide, you will minimize their resistance.
The difficulty with that, however, is that overly large shapes consume valuable routing space and may limit the amount of space for other voltage shapes. A design which has the properly sized power and ground shapes will be more compact and use fewer layers than one which arbitrarily uses overly large planes or traces. The intent of PI-DC analysis is to inform a designer that the board design's power and ground shapes are adequate, but not overly large.
Another consideration for IR drop is the fact that the amount of power consumed is
I2R – so a small increase in current through a resistance causes a large increase in power consumption. This can manifest itself as thermal problems where the design heats up significantly because the power and/or ground shapes are not large enough to accommodate the current passing through them. By ensuring very small IR drop through power and ground shapes, power consumption in those shapes is minimized.
At the extreme, if a shape is resistive enough (very narrow and long) and has sufficient current flowing through it, that shape essentially becomes a 'fuse', thereby melting the copper shape and causing the design to fail – and possibly presenting a dangerous situation. The IPC-2152 standard for PCB current carrying capacity addresses this issue, but with pessimistic assumptions (no nearby thermally conductive copper to help draw heat away, for instance) and designers often apply that specification using the most conservative assumptions, such as only allowing a minimum temperature increase. While PI-DC cannot replace the IPC-2152 standard as a guideline for thermal considerations, it can give valuable insight into how a design can safely be optimized by studying the voltage drops and current densities of the power delivery system. A design that is optimized for the lowest current density and voltage drop between the sources and all loads will also generate less heat and have less chance of thermal issues.
Another aspect PI-DC analysis addresses is the number of vias used for power delivery. The problem is quite similar to that of sizing the copper shapes properly: if there are not enough vias, voltage is lost and power is wasted through IR drop, but if too many vias are used, valuable routing real estate is wasted. In particular, if too many vias are used for a particular voltage path, those vias pass through shapes on other layers and reduce their copper cross-section, thereby causing problems for those other voltages. In the same way as correctly dimensioning shapes, analyzing the voltage at the load points allows proper via sizing and/or numbering.
Finally, there is a significant advantage in simulating the final design exactly as it appears physically, to ensure it is optimized. PI-DC simulation provides a final check that connectors and regulators are sized appropriately, in case loads have been dropped or added during the design process, for example.
In the absence of reliable data on the voltage drop through a PCB's various power shapes, ground shapes and vias, a designer is forced to be conservative by using excessive plane shapes, trace sizes and vias, which consume valuable design real estate and increase layers and the design form factor. The Altium PDN Analyzer provides accurate information about a design’s DC power distribution suitability in an easy-to-use and straightforward manner to enable designers to make the most efficient power distribution designs possible.
Not only are the results suitable for final design verification, but they can also be used in the planning stages of a design to architect power delivery as efficiently as possible in advance. PI-DC is an invaluable tool in achieving the most efficient and robust power delivery network possible, the PDN Analyzer makes running that simulation and analysis process straightforward, intuitive and efficient.
Among these and other advantages that the PDN Analyzer brings to your PCB designs, it also delivers the following benefits:
In its most very basic form, a board layout that will be subject to PI-DC analysis might be composed of a Voltage Regulator source and its load, with interconnecting copper areas of various shapes and track widths.
The PDN Analyzer panel interface (Tools » PDN Analyzer) visually emulates a Power Source to Load circuit net that incorporates tangible Power and Ground paths – much as shown in the above circuit and also the conceptual block diagram (Fig. 1). The application automatically extracts all physical and electrical information (netlist, devices and layer shapes, etc) from the currently active PCB design, which provides data for the PI-DC simulation engine.
Here, the voltage source is the output of U1 (5V between pins 3 and 2), and the load is a specified current through RL (0.1A). Once the initial parameters have been entered via the interface (source/load voltages and currents, etc) and the simulation has been run, the resulting analysis data is graphically modeled in the PCB editor as a rendered 2D or 3D image.
The PDN Analyzer PI simulation can be set to show Voltage (IR Drop, above image) or Current Density (below image) results for all applicable board layers.
► See the PDN Analyzer example guide for a complete description of using the PDN Analyzer and interpreting its results.
The PDN Analyzer application is added to Altium NEXUS by installing the PDN Analyzer Extension. Its functionality is enabled with a matching software License.
The PDN Analyzer is installed (and updated) from the software's Extensions & Updates view, which is accessed from the User drop-down menu () located at the top right of the Altium NEXUS GUI.
Select the Purchased tab in the Extensions & Updates view, locate the PDN Analyzer icon and then click its button to download and install the extension. Restart Altium NEXUS to enable the application.
Once installed, the extension will appear under the Extension & Updates view’s Installed tab. The PDN Analyzer tool is available from the Altium NEXUS Tools menu as PDN Analyzer when a Schematic or PCB project document is open. Note that if the PDN Analyzer is unlicensed, a related error message will appear – see below for license activation steps.
► See the Altium NEXUS Extensions page for more detailed information about installing and managing extensions.
The PDN Analyzer can be licensed using any of Altium's standard License schemes; by activating an On-demand or Standalone license from Altium's License Server, or from an internal network Private License Server.
To locate a license served by Altium's licensing portal, open the Altium NEXUS License Management view (select License Management from the menu) and scan through the Available Licenses list for an On-demand or Standalone PDN Analyzer powered by CST® license entry. Select the desired license and type (On-Demand/Standalone) and click the Use link to activate that license for the PDN Analyzer extension.
When the license is activated, its Assigned Seat Count number will increment and the entry's Used column will include a 'Used by me' entry.
► See the Altium NEXUS Licensing page for more information on Altium licensing and types of licenses.
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