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Parent page: Design Rule Check (DRC)
In the folder-tree pane on the left side of the dialog, each of the design rule categories whose rule types can be checked are listed under the Rules To Check folder. Click on this top-level folder to list all checkable rule types on the right side of the dialog. Alternatively, click on a specific category to list only those design rule types associated to that category. Use the dialog to enable/disable Online (where available) and/or Batch Mode checking for each rule type you want to check.
Online Design Rule Checking runs in the background, in real-time, flagging and/or automatically preventing design rule violations. This is especially helpful when interactively routing your board to immediately highlight clearance, width and parallel segment violations. For a rule to be subject to the Online DRC, the following three requirements must be met:
If any objects are found to be in violation of an applicable design rule that is enabled for online checking, they will be highlighted in the design space in accordance with defined violation display options.
Whereas Online DRC only detects new violations - violations that are created after the feature is enabled - Batch DRC allows a check to be manually run at any time during the board design process. So while good designers know the value of Online DRC, they also know that board design should begin and end with a Batch DRC.
Enable rule types for batch checking in the Design Rule Checker dialog as required (refer back to the Configuring the DRC section). Various additional options are available when running a Batch DRC, including the ability to generate a report file. These options are accessed by clicking on the Report Options folder in the folder-tree pane of the dialog. Two key options (highlighted in the following image) are:
A batch-mode DRC is initiated by clicking the Run Design Rule Check button at the bottom-left of the dialog. After the check has completed, all violations are listed as messages in the Messages panel. If you opted to do so, a DRC report will be created and automatically opened (if configured to do so) as the active document in the main design window. The report lists each rule that was tested as specified in the Design Rule Checker dialog. Rules that are not present in the design are not tested.
Enabling the Create Report File option in the Design Rule Checker dialog will generate a DRC report upon execution of a Batch DRC. Options available on the PCB Editor - Reports page of the Preferences dialog allow specification of report format, and whether the report is automatically displayed after generation.
Supported formats are:
The report lists each rule that was tested during the batch checking process as specified in the Design Rule Checker dialog. Each violation that was located is listed with full details of any reference information, such as the layer, net name, component designator, and pad number, as well as the location of the object.
Checking the design against specified design rules is one thing, but what happens when one or more of those rule are violated? Whether running Online DRC during design or manually running a Batch DRC, there needs to be some visual indication of where such rule violations are occurring. The PCB Editor includes powerful violation display options to indicate where violations exist in a clear, visual way.
Most design rules that can be included in either Online and/or Batch design rule checking have associated custom violation graphics - appearing within the design space when a particular rule is violated. These graphics provide a visually cleaner DRC landscape. When a particular design rule is violated, the associated custom violation graphics (where applicable) are only drawn on the layer(s) involved with that violation.
In some cases, the graphic shows not only where the violation is occurring, but also why - displaying the constraint value defined for the rule and indicating how the offending primitive(s) are either below or above this value.
Other graphics, including those used to represent violations of Net Antennae, Short-Circuit, Un-Routed Net, Room Definition, Layer Pairs and Vias Under SMD rules will be a graphic, as there is no definable constraint value to be displayed.
In addition to the custom violation graphics, a violations 'overlay' is available for setup and use. The overlay draws over design primitives. You have a choice of what pattern to display on the primitives from a selection of styles.
Using a combination of the two violation display types can prove useful in terms of providing a 'coarse' and 'fine' indication of violations. When zoomed out, the violation overlay can flag where a violation exists, then zoom in to view the detail delivered by the associated custom violation graphic.
Control over how DRC violations are displayed - using the custom violation graphics and/or a defined violation overlay - is specified on the PCB Editor - DRC Violations Display page of the Preferences dialog.
Options available allow you to:
Choose the display style used, on a per-rule basis, in the Choose DRC Violations Display Style region. Enabling the Violation Details option for a rule type will use the associated custom violation graphics to display the DRC violations of that rule. Enabling the Violation Overlay option will display the violations using the specified overlay style.
To give further flexibility when displaying rule violations in the design space, the two violation display types - violation details (custom violation graphics) and violation overlay - have separate associated system colors. This allows you to differentiate between the two using different, distinct colors. Color assignment is performed in the System Colors section on the Layers & Colors tab of the View Configuration panel:
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