Parent page: More about Schematics
Design Directives are objects that are placed on the schematic during design capture, providing a way of specifying instructions to be passed to other parts of the software. A variety of Design Directives are available, for use in the following two ways:
- Directives associated with the compilation of source schematic documents.
- Directives used to pass information defined on a schematic sheet through to the PCB.
The following sections take a closer look at these areas and the associated directives.
Designs evolve over time and are captured in stages. As each stage is bedded down, it's not uncommon to want to check them in isolation to the rest of the design. Compilation of an individual schematic document (or the entire project) at intermittent stages in the capture process will often yield a number of error messages, caused by circuitry that is yet to be captured, or interface wiring between circuit fragments that are still incomplete. Such messages are of no real value since they only create noise around the real information. The quickest and easiest way to suppress these compilation errors is by placing No ERC, or Compile Mask directives.
No ERC Directive
Object page: No ERC
The No ERC directive is placed on a node in the circuit to suppress all reported Electrical Rule Check warnings and/or error violation conditions that are detected when the schematic project is compiled. Use a No ERC directive to deliberately limit error checking at a certain point in the circuit that you know will generate a warning (such as an unconnected pin), while still performing a comprehensive check of the rest of the circuit.
The No ERC directive supports a number of different styles, and can be displayed in any color. Use this ability to reflect the design intent for this point in the circuit.
Choose a No ERC style that best reflects its function at that point in the circuit.
The No ERC directive has two modes of operation:
- Suppress All Violations - in this mode, all possible warnings and/or error conditions are suppressed. The directive is often referred to as a Generic No ERC directive, in this mode.
- Suppress Specific Violations - in this mode, only the selected warnings or error conditions are suppressed; any other warnings or errors will be detected and reported. The directive is often referred to as a Specific No ERC directive, in this mode.
How many times have you encountered a warning about a net 'not having a driving source', only to find that the message can be safely ignored? Perhaps an input pin is fed from a connector, the pin of which is nominally passive and the driving signal only present when an external cable is plugged in? Maybe the net is sourced from a pull-up resistor or switch, again passive in nature? One of the following strategies could be adopted to resolve this warning:
- You could change the electrical characteristic of a source pin on the net. This is a fix rather than suppression, but as it involves a change to a pin's default mode of operation, it could create trouble further down the track. For example, consider wiring changes made to a design, in which the graphical display of pin direction is not enabled. Such changes might result in an output being connected to a pin of a passive device. If the pin of that device has been set electrically as an output (to alleviate previous driving source warnings), then you will have created a connection violation.
- You could set the report mode for the associated violation check - defined on the Error Reporting tab of the Options For Project dialog - to No Report. This disables the check of this particular violation, but you would also not be able to catch any genuine errors elsewhere in the design.
- The third (and arguably best) option is to place a No ERC directive on the net. You are not changing the design in any way, other than to suppress warning message 'noise' that you know is not a problem.
Place No ERC directives on nets you know will cause 'no driving source' warnings.
A No ERC directive can be placed into a schematic document in a number of ways:
Choose a violation to suppress, then click OK to place a tailored, specific No ERC directive on that point in the circuit.
- Place a specific No ERC directive on a point in the circuit that is already showing a violation, by right-clicking over a violating object in the workspace (highlighted by a wavy colored line) and choosing the Place NoERC to Suppress command, from the context menu.
Using the right-click context menu to place a specific No ERC directive.
- Place a specific No ERC directive on a point in the circuit that is already showing a violation, by right-clicking on a warning/error in the Messages panel, choosing the Place Specific NoERC for this violation command, then jumping straight to that point in the schematic and placing a No ERC directive configured to suppress that warning/error.
Using the right-click context menu in the Messages panel to place a specific No ERC directive.
During placement, and while the No ERC object is still floating on the cursor, the following editing actions can be performed:
- Press the Tab key to access the No ERC dialog, from where properties for the No ERC object can be changed on-the-fly.
- Press the Spacebar to rotate the No ERC object anti-clockwise or Shift+Spacebar for clockwise rotation. Rotation is in steps of 90°.
- Press the X or Y keys to mirror the No ERC object along the X-axis or Y-axis respectively.
Once placed, a No ERC directive can be modified in a number of ways:
- From the No ERC dialog. Aside from general properties, such as colouring, style, and rotation, a directive can be switched from Specific to Generic by changing the Electrical Properties option from Suppress specific violations (Specific), to Suppress all violations (Generic), and vice-versa.
Change properties for a No ERC directive through the associated No ERC dialog. You can quickly
switch between suppressing specific violations, and suppressing all violations (roll over the image
to see the change to the dialog).
- From the SCH List panel, or SCH Inspector panel. In particular, the ability to quickly switch between mode (generic or specific) is controlled by the Suppress Specific Violations option.
Change properties for a selected No ERC directive through the SCH List or SCH Inspector panels.
- From the NoERC Manager dialog. Accessed using the Tools » NoERC Manager command from the main menus, this dialog enables you to review and edit all the No ERC directives used across the entire project. The NoERC Manager dialog allows you to move through the list of nets with directives applied and edit any number of No ERC directives. When editing is complete, click the Generate ECO button to apply all of the changes.
Use the NoERC Manager dialog to review and edit the directives across the entire design. Directives that have been modified are
highlighted; changes are then applied via the ECO system.
Rather than deleting a No ERC directive, it can be simply made inactive (disabled in the eyes of the Compiler). This state can be changed by toggling the directive's Active property - available through any of the methods of editing. An inactive No ERC directive will appear grey in the workspace.
If you need to temporarily remove use of a No ERC directive, simply render it inactive, rather than deleting it.
Compile Mask Directive
Object page: Compile Mask
No ERC directives are great for suppressing a low number of violating pins, ports, sheet entries, or nets within a design. But in some cases, it may be desirable to remove an entire section of the design; including components. Use a Compile Mask directive (Place » Directives » Compile Mask command) to effectively hide the area of the design it contains from the Compiler, allowing you to manually prevent error checking for circuitry that may not yet be complete and you know will generated compile errors. This can prove very useful if you need to compile the active document, or project, to check the integrity of the design in other specific areas, but do not want the 'noise' of compiler-generated messages associated with unfinished portions of the design.
As its name suggests, this directive simply instructs the Compiler to ignore any objects that fall completely within the bounds of the defined mask. Place the mask exactly as you would a note or rectangle object.
Consider the example schematic circuitry in the following image, where the wiring to the LCD1 device is not yet complete. Compiling just this schematic (Project » Compile Document) will result in numerous violation messages (also shown), each of which is caused by the incomplete circuitry. Hover over the image to see the effect of placing a Compile Mask directive around the incomplete circuitry. These violations will be ignored by the Compiler, while the rest of the circuit on the schematic - which is completely wired - is checked. Notice that objects that are truly masked - those that completely fall within the bounding rectangle of the mask - will appear greyed-out.
Roll over the image to show the effect of using a Compile Mask directive to hide compiler violations due to incomplete circuitry.
Application to Simulatable Designs
Because all elements of a design covered by a Compile Mask directive are invisible to the design compiler, they will be omitted from the design. This feature can be put to great use when simulation is included as part of the design flow.
Voltage and Current sources are necessary elements when running circuit simulations, but they have no place on the completed PCB. By applying a small amount of planning to the structure of the circuit, it is usually possible to group all simulation-specific components in one section of the design - a section that can then be easily covered by a Compile Mask directive.
When the circuit is used for simulation, the Compile Mask directive is disabled to reveal the simulation-specific components. Once the circuit is verified and ready for inclusion in the design, the Compile Mask directive can be re-enabled, so that the simulation-specific components are excluded from the design. If the design should ever need to be changed again in the future, another simulation pass can be quickly executed prior to signoff by simply disabling the Compile Mask directive (to reveal the simulation-specific components again).
Initially, the Compile Mask directive is disabled, making the circuit ready for simulation. Roll over the image to show the Compile Mask directive enabled,
thereby hiding the simulation sources from the design.
Object page: Parameter Set
As a Unified Design Environment, Altium Designer provides the ability for PCB requirements to be defined prior to laying out the board. This is achieved by adding and specifying parameters to objects placed on the schematic sheet(s).
For certain schematic design objects - such as components, sheet symbols, ports, etc - this simply involves adding the relevant parameter(s) as part of that object's properties. For net objects such as wires and buses, parameters cannot be added directly as a property of the wire or bus. Instead, the parameters required to hold the information are specified using dedicated design directives.
The following information can be specified, using directives, and will be transferred to the appropriate PCB-based definitions during design synchronization:
- PCB layout constraints
- Net classes
- Differential pairs
By including design directives within the Schematic, design engineers can specify explicit design constraints, and it ensures the Schematic remains the master record of the design. Any amendments to the design would be carried out on the schematic side only, and pushed across to the PCB. This can become particularly important when multiple people are working on the design - especially if they are geographically separated. Rather than attempting to communicate with one another through chains of emails, or phone calls, the person capturing the design can ensure that particular constraints are indeed used during the layout phase.
At the heart of this functionality is the Parameter Set directive.
A Parameter Set directive.
This acts as a container for any number of parameters targeting the net that the Parameter Set directive is attached to. A default Parameter Set directive, one that is devoid of parameters, can be placed (Place » Directives » Parameter Set) and the relevant parameter(s) added to it. However for the three types of information listed previously, there are predefined Parameter Set directives that can be used (available from the same sub-menu). The following sections take a closer look at using these parameter-based directives.
Placing Parameter Set Directives
Place a directive of this type by choosing the Place » Directives » Parameter Set command from the main menu, or when right-clicking within the workspace. When placing a default parameter set directive, there will be no existing parameters. A parameter set is a design directive that allows design specifications to be associated to a net-type object within a schematic design. For example, use a parameter set to declare two nets to be members of a differential pair. It is the presence of specifically named parameters in the parameter set that the software uses to determine which design directive you are placing.
In addition to user-defined paramater directives, a rule-based parameter directive is defined from the Choose Design Rule Type dialog, accessible from a parameter's associated properties dialog. Access involves the following:
- Press Tab before placing the PCB Layout directive, or double-click an already placed PCB Layout directive, to display its Parameters dialog.
- Select the entry for the rule (if multiple exist) and click the Edit button in the Parameters dialog to open the Parameter Properties dialog.
- Next, click the Edit Rule Values button to access the Choose Design Rule Type dialog from where the PCB rule(s) can be specified.
Editing the value for a rule in a PCB Layout directive.
Use the Choose Design Rule Type dialog to choose the rule that you wish to add as a rule parameter to the directive. Double-clicking on a rule type will give you access to the relevant Edit PCB Rule (From Schematic) dialog, from where you can define the constraints for the rule.
Specifying the constraints for a chosen rule.
The entry for the parameter's Value field will be the rule type chosen, along with the specified constraints. The following image illustrates several defined rule parameters for a PCB Layout directive.
Multiple rule constraints defined for a particular net, courtesy of a PCB Layout (Parameter Set) directive.
When the design is transferred to the PCB, through the Synchronization process, the relevant design rules will be created, based on the information contained within a directive. The word Schematic is used in the name for each generated rule, to distinguish the source of that rule.
Generated design rules on the PCB side.
Synchronization between a rule directive and its corresponding PCB rule is maintained through use of Unique IDs. When adding design rule parameters to objects on a schematic, a unique ID is given to each. The same IDs are given to the corresponding design rules that are created in the PCB. With this Unique ID, the constraints of a rule can be edited on either the schematic or PCB side and the changes pushed through upon synchronization.
Defined rules are kept synchronized between schematic and PCB through the use of Unique IDs.
Net Class Directive
This is essentially a pre-configured Parameter Set object, which can be associated to a net object within a schematic design. Net Class directives enable you to create user-defined net classes on the schematic. When a PCB is created from the schematic, the information in a Net Class directive is used to create the corresponding Net Class on the PCB. To make a net a member of a net class, attach a Net Class directive to the relevant wire, bus, or signal harness, and set the directive's ClassName parameter to the name of the desired class.
Place a directive of this type by choosing the Place » Directives » Net Class command from the main menus. A newly-placed Net Class directive contains a default parameter with name ClassName, and undefined value. Simply edit this parameter's value to define the name for the net class.
To ensure Schematic defined Net Classes are propagated to the PCB, the following options must be set in the Options for PCB Project dialog:
- Enable the Generate Net Classes option located in the User-Defined Classes region of the dialog's Class Generation tab.
- On the dialog's Comparator tab, set the Differences Associated with Nets » Extra Net Classes checking mode to Find Differences.
To propagate Net Class directives to the PCB, two project options need to be configured. First, enable the Generate Net Classes option on the Class Generation tab. Roll
over the image to show the Comparator tab, where you will need to set the Extra Net Classes option to Find Differences.
When the design is transferred to the PCB, through the Synchronization process, the relevant net classes will be created, based on the information contained within a directive.
Example generated Net Class on the PCB side.
Differential Pair Directive
This is essentially a pre-configured Parameter Set object, which allows you to define a differential pair on the schematic. Attach a directive of this type to both the positive and negative nets of the intended pair. The nets themselves must be named with the suffixes of _P and _N respectively.
Place a directive of this type by choosing the Place » Directives » Differential Pair command from the main menus. The directive contains a single parameter entry, with Name: DifferentialPair and Value: True. Each pair of directives (one for the positive net, one for the negative) of this type will yield a single differential pair object when transferred to the PCB.
Example placement of Differential Pair directives on a schematic. Two directives are required - one on the positive net, and one on the negative net, for the pair.
When the design is transferred to the PCB, through the Synchronization process, a single differential pair object is created from each pairing of directives. The name of a generated differential pair object on the PCB side will be the root name for the net pair on the schematic. For example directives added to D_N and D_P on the schematic, will generate a differential pair object on the PCB with the name D. Each resulting differential pair object will be added to the default Differential Pair class: <All Differential Pairs>. You can rename differential pair objects on the PCB side only.
Generated differential pair objects can be quickly verified using the PCB panel, configured in Differential Pairs Editor mode.
Verify creation of differential pairs on the PCB side, using the PCB panel, configured in its Differential Pairs Editor mode.
Object page: Blanket
Parameter Set directives can only target the specific net that they are attached to, but when combined with a Blanket directive, their scope can be expanded to cover all nets within the blanket.
Place a directive of this type by choosing the Place » Directives » Blanket command from the main menus. When placing a blanket, you can either define a simple rectangular shape, or a polygonal-shape. The latter gives more precise control over coverage of the required net objects on a sheet.
The blanket identifies the nets of interest - place a parameter set directive (Place » Directive) anywhere on the edge of the blanket, to apply design requirements to those nets. To apply the perimeter directive to a net under a Blanket directive, an object associated to that net - a pin, a port, a net label, a power port, a wire/bus/harness segment (including both ends) - must fall within the bounds of the blanket. Note that for net identifiers, such as net labels, the hotspot must be within the blanket. If member nets do not come across into the PCB net class as expected, try adjusting the area of the blanket accordingly.
An example of using a Blanket directive to apply a Net Class directive (Parameter Set directive) to nets within the blanket.
Example usage of a blanket directive can include:
- Attaching a PCB Layout directive to a blanket object, to have its rule parameters applied to each individual net covered by that blanket.
- Attaching a Net Class directive to a blanket object, to create a net class whose members are the individual nets covered by that blanket.
- Attaching a Differential Pair directive to a blanket object, to create differential pair objects based on differential nets within the confines of that blanket.
- Attaching a Net Class directive AND a PCB Layout directive to a blanket object. The PCB Layout directive's rule parameters will target that net class, rather than each individual net. When importing the changes into the PCB document, this results in a single design rule being created (per parameter), with a scope set to target the net class.
Indirect (Parameter-based) Directives
Parameter Set directives are necessary when targeting design objects in the Schematic that can't contain parameters, but for those objects that can, design directives can be applied indirectly by adding (and defining) them as parameters to the relevant schematic object. In essence, they are parameter-based directives.
Examples of how parameter-based directives could be used would include limiting the height of a particular component, or adding a clearance constraint targeting all objects in the design. The required parameter that defines the constraint is added to the object as a rule in exactly the same way that parameters are added to a PCB Layout directive.
When synchronized with the PCB, parameter-based directives that have been added to objects in the Schematic will become PCB design rules. The scope of the corresponding PCB design rule will be determined by the nature of the object to which the pa rameter was first assigned. The following table summarizes the Schematic parameter-to-PCB rule scope options that are supported, including those defined by placing PCB Layout directives.
In each case, the method of adding a rule-based parameter is the same. From the respective tab or dialog, simply perform the following:
- Add a parameter as a rule.
- Select which rule type to use.
- Configure the constraints for the chosen rule type.
Specifying Component Classes
In a similar vein, component classes can be defined on the schematic by adding a ClassName parameter to targeted components and setting its value to the desired class name. When the design is transferred to the PCB, the defined component classes will be created.
To ensure Schematic defined Component Classes are propagated to the PCB, the following options must be set in the Options for PCB Project dialog:
- Enable the Generate Component Classes option located in the User-Defined Classes region of the dialog's Class Generation tab.
- On the dialog's Comparator tab, set the Differences Associated with Components » Extra Component Classes checking mode to Find Differences.
To propagate Component Classes to the PCB, two project options need to be configured. First, enable the Generate Component Classes option on the Class Generation tab. Roll
over the image to show the Comparator tab, where you will need to set the Extra Component Classes option to Find Differences.
Controlling the Printing of Directives
By default, all design directives are included during printing of the schematic sheets. This can, however, be changed:
Control the printing of directives as required. For No ERC directives, you can opt to print certain symbol styles, while excluding others.