The practical performance of a PCB design layout depends on a multitude of factors, many of which can be predicted, to a reasonable degree, through a range of PCB design analysis tools such as post-layout Signal Integrity analysis. What's often neglected however, or simply relegated to a 'rule of thumb' methodology, is developing the most effective layout design for board's DC Power Delivery systems. This is the judgment applied to the design of a board's copper areas that provide both the DC supply rails to the circuitry, and their ground or common return path to the DC supply source. The desired outcome is an efficient design that maintains the integrity of the design's DC power layout.
With modern digital designs featuring high-speed circuitry, multiple devices, densely populated boards and multiple supply rails, the demands placed on a design's DC power distribution network warrants a more analytical approach to its design. The DC analysis of a Power Delivery Network (PDN), or the results of its DC Power Integrity (PI-DC), is basically aimed at ensuring that adequate copper has been provided in the path from the voltage sources to the loads – in other words, that the planes, traces and vias on the board of are of sufficient size (and characteristics) to meet the power consumption requirements of the devices on the board.
Fortunately, the guesswork can be removed from the assessment of a PCB's power delivery network (PDN) through the use of a DC Power Integrity (PI-DC) simulation tool, which analyzes a board design's DC performance based on its electrical and physical properties. Such a tool is now available for Altium Designer as the Altium PDN Analyzer powered by CST® (Computer Simulation Technology).
Date: 3 May 2017
||Fix bug that caused PDNA Batch Mode crashes with large simulation count.
||Fix bug that caused internal layer planes to disappear during results viewing.
Date: 15 February 2017
||Added support to display the voltage relative to the nearest ground when probing. Both the VCC and GND voltages are reported.
||Added ability to set up config files for many power rails and run them as a batch.
||Updated the battery symbol.
||The output .csv file now uses comma delimiters.
||Disabled unnecessary processing of Mechanical layers in ODB++
||Updated PDN Analyzer so ODB++ is only regenerated within a session if the layout changes.
||Added ability to navigate/zoom in on areas of highest current density.
||Fixed regression bug that caused mid-layer polygon object to not be displayed.
||When probing the signals, lose the ability to maneuver in 3-D (shift + right mouse doesn't rotate the image).
Date: 22 August 2016
(Previously released version 22.214.171.124)
Altium and CST® have updated the PDN Analyzer extension. This version fixes cases where connections were missing between the pads of capacitors and their nets after simulation, and analysis was failing on a design due to meshing issues.
Date: 20 July 2016
(Previously released version 126.96.36.199)
Altium and CST® have updated the PDN Analyzer extension. This version fixes cases where having semicolons (“;”) in components’ comments section caused a simulation failure.
Date: 13 July 2016
(Previously released version 188.8.131.52)
Altium and CST® have updated the PDN Analyzer extension. This version fixes some cases where Version 184.108.40.206 could not load existing configuration files.
Date: 7 July 2016
(Previously released version 220.127.116.11)
Altium and CST® have updated the PDN Analyzer extension to add new key capabilities, and resolve a number of simulation and interface issues. Below is a list of changes made to the current release of the extension and the issues that have been addressed.
Added the ability to view voltages and current densities of vias. Vias are now represented with appropriate color coding just as other power and ground shapes are. Display of vias can be toggled as are layers.
Added a ‘via wall thickness’ variable in the setup to comprehend vias as hollow objects. The effective area of vias is derated appropriately to represent their increased resistance due to the missing material. See the Via Wall Thickness section of the documentation for more information.
Improved the configuration file (
*.pidc_confg) format by listing components with their full identifier, and not just by their reference designator. This is a significant change directed at making the Analyzer software more robust and capable, but will affect the portability of configuration files, since they will only be valid for the specific PCB from which they were generated.
- Improved reporting of simulation failures by providing more information about the cause, rather than just cryptic error codes.
- Added preemptive disabling of simulations that will result in failures, when possible.
- Resolved simulation failure on ‘PWR580B’ design using virtual components.
- Resolved a Configuration loading issue where the changed ODB caused a virtual component mismatch.
- Fixed Analyzer use of ODB layer names instead of user layer names.
- Resolved customer design that fails for 0 thickness of ‘Plane2_1’, which doesn't exist.
- Fixed updating of Recent Designs list, which did not include a config that has been saved under a new name.
- Improved the separation of ‘Properties’ from ‘Criteria’ in the Source and Load selection dialog.
- Resolved erroneously high current density being reported at connection to source.
- Fixed layers not being shown for thick designs.
- Resolved simulation failure when devices touch multiple power rails.
- Fixed component selection, which prevented choosing the correct part if “j” has been typed after selecting the drop down.
- Fixed Results panel not showing voltage results at load.
- Resolved simulation failure when excitation has same pin designator for two pins.
- Fixed wording when simulation fails from “Simulation ran failed…” to “Simulation failed…”.
- Resolved simulation failure when multiple pins have been used on the source or load.
- Separated the “Properties” from the “Criteria” better in source and load selection dialogs.
- Fixed issue where the power path was made invalid when loading configurations.
Date: 23 May 2016
(Previously released version 18.104.22.168)
Altium has updated the PDN Analyzer extension to resolve an existing issue with designs which use the same pin designator for multiple pins. Below is detail of the issue addressed and changes made to the current release of the extension.
In previous versions of PDN Analyzer, using the same designator for multiple pins would cause the simulation to fail with the following (or similar) error messages:
- [Error] <<error>>
- [Error] solver stopped due to exception:
- [Error] Traceback (most recent call last):
- [Error] File "<string>", line 1, in <module>
- [Error] File "altium_plugin\pidc.py", line 507, in create_plb_file
- [Error] File "altium_plugin\pidc.py", line 494, in create_ICs
- [Error] File "altium_plugin\pidc.py", line 455, in __init__
- [Error] KeyError: ('1',)
- [Error] <<end>>
This issue has now been resolved - simulations will complete successfully if the same pin designator is used for multiple pins.
Date: 13 May 2016
(Previously released version 22.214.171.124)
Altium has updated the PDN Analyzer extension to resolve an existing issue with designs which have spaces in their component names. Below is detail of the issue addressed and changes made to the current release of the extension.
In previous versions of PDN Analyzer, component names with spaces would cause the simulation to fail with the following (or similar) error messages:
- [Error] Flex_6946.PcbDoc PDN Analyzer solver stopped due to exception:
- [Error] Flex_6946.PcbDoc PDN Analyzer Traceback (most recent call last):
- [Error] Flex_6946.PcbDoc PDN Analyzer File "<string>", line 1, in <module>
- [Error] Flex_6946.PcbDoc PDN Analyzer File "altium_plugin\pidc.py", line 507, in create_plb_file
- [Error] Flex_6946.PcbDoc PDN Analyzer File "altium_plugin\pidc.py", line 494, in create_ICs
- [Error] Flex_6946.PcbDoc PDN Analyzer File "altium_plugin\pidc.py", line 360, in __init__
- [Error] Flex_6946.PcbDoc PDN Analyzer AttributeError: 'NoneType' object has no attribute 'n_pins'
This issue has now been resolved - simulations will complete successfully if net names have spaces in them.
Date: 11 May 2016
(Previously released version 126.96.36.199)
Altium has updated the PDN Analyzer extension to resolve existing issues and preclude analysis with invalid setup parameters. One primary aim is to eliminate the possibility of performing a lengthy PDN Analyzer simulation only to find it was invalid due to an erroneous setup parameter.
Below is a list of the issues addressed and changes made to the current release of the extension.
Check that load has non-zero amperage: entering 0A as a current sink is now not allowed.
Ensure valid stackup before enabling simulation. Checks stackup parameters and disables simulation if any are not valid:
- Invalid dielectric constant (<1).
- 0 thickness for dielectric or conductor.
Ensure a maximum of 2 nets in the path between the source and load power nets. If there are more than 2 nets between the source and load power nets, the user will be prompted by; “Many nets between source and loads, proceed with simulation?” (Yes, No). This warns the user that they may have built an erroneous path (see Source to Load path section in the PDN Analyzer Guide).
Report the cause of any red exclamation marks (!), so as to inform the user what has failed. If a red exclamation mark is shown, the failure will be printed in the messages dialog:
- "Error: Source <U#> exceeded max allowed PWR supply DC current magnitude. Allowed: x.xxxA, Actual: x.xxxA"
- "Error: Source <U#> exceeded max allowed PWR pin current magnitude. Allowed: x.xxxA, Actual: x.xxxA"
- "Error: Source <U#> exceeded max allowed GND pin current magnitude. Allowed: x.xxxA, Actual: x.xxxA"
- "Error: Load <U#> did not meet minimum required DC Voltage magnitude. Minimum: x.xxxV, Actual: x.xxxV"
The maximum current densities reported by the auto-scale did not agree with maximum current density found when probing. For example, auto-scaling showed the maximum current density as 1.2GA/m2, while probing indicated that the largest current density was 0.2GA/m2 (the internal .json file verified a maximum current density of 1.2GA/m2). The software issue has been resolved, and probing now agrees with that reported by the auto-scale.
PDN Analyzer was not interpreting strings correctly: when converting the string "0Rab", if a is zero, the zero is discarded. This is now resolved.
Older pcbdoc's do not have a SimulationDummy.PcbDoc.htm file, so the simulation failed. This issue has been fixed.
Collection of data on errors. If you have agreed to participate in the Altium Product Improvement Program, the following data will be collected:
- If the simulation run was successful or not.
- Error codes and messages.
- Net count in the path, load count, source count, ODB file size, ODB++ generation time, and simulation run server time.
Provided as a downloadable Altium Extension application, the PDN Analyzer integrates directly with Altium Designer to allow PI-DC simulation and analysis of the current PCB project. Since the PDN Analyzer functions within Altium Designer there are no manual data import/export requirements, data conversions or separate applications to be run – simply start the PDN Analyzer from Altium Designer's Schematic or PCB editor, set the desired test parameters and run the simulation. The results are primarily delivered through 2D/3D modeling of the circuit board copper layout, allowing a quick assessment of the results and the opportunity to easily perform exploratory 'what if' testing of the PCB layout design.
The PDN Analyzer interface shown with the Altium Designer Spirit Level example PCB, and the results of a PI-DC Voltage Drop simulation of its Top layer GND net return for the VCCINT supply.
Power Integrity essentials
In essence, the PI-DC (or 'IR drop') problem is fairly straightforward: the resistance embodied in the board's power supply shapes (traces, polygons, planes etc) consumes power and voltage, robbing those from the various loads. As you would expect, the IR issues will increase in complexity with the number of loads on the supply through interaction in the power and ground copper paths.
Figure 1: A basic block diagram of the power and ground shapes, and the applied loads.
Figure 1 (above) shows a simple block diagram of a circuit's power source, and its power and ground shapes (traces and planes) that deliver power to the various loads (memory, microcontrollers, etc.). Note that all the loads are tied to the same power and ground shapes, and depend on those shapes to provide their operating voltage(s). In general, we tend to assume that those power and ground shapes have 0Ω resistance, which isn’t necessarily true, and that assumption can cause problems. Because relatively large currents are often involved, even small resistances in the power and ground shapes can cause significant power consumption (loss) and voltage drops.
Figure 2: 'IR Drop' effects
Figure 2 demonstrates an example of the problems that can arise if the resistance of the power and ground shapes aren’t properly considered. Even though each shape has a relatively small resistance of only 0.25 (¼) ohm, they have caused the voltage at the load to drop from 5V to 4.5V. The designer has to be aware of this drop and ensure it can be accommodated, or change the design to lessen it, to ensure that that the final design will not fail in the field.
The problem, however, seems easy to solve – simply make the power and ground shapes short or large enough to represent an insignificant resistance, using the following relationship:
R = ρ * L/A, where:
R is the total resistance of a shape (trace or plane)
ρ is the resistivity of the material used for the shape (typically copper,
ρ ≈ 1.7µΩ-cm)
L is the length of the shape
A is the cross-section area of the shape (width
Put simply, if you make your power and ground shapes short, thick and wide, you will minimize their resistance.
The difficulty with that, however, is that overly large shapes consume valuable routing space and may limit the amount of space for other voltage shapes. A design which has the properly sized power and ground shapes will be more compact and use less layers than one which arbitrarily uses overly large planes or traces. The intent of PI-DC analysis is to inform a designer that the board design's power and ground shapes are adequate, but not overly large.
Another consideration for IR drop is the fact that the amount of power consumed is
I2R – so a small increase in current through a resistance causes a large increase in power consumption. This can manifests itself as thermal problems where the design heats up significantly because the power and/or ground shapes aren’t large enough to accommodate the current passing through them. By ensuring very small IR drop through power and ground shapes, power consumption in those shapes is minimized.
At the extreme, if a shape is resistive enough (very narrow and long) and has sufficient current flowing through it, that shape essentially becomes a 'fuse', thereby melting the copper shape and causing the design to fail – and possibly presenting a dangerous situation. The IPC-2152 standard for PCB current carrying capacity addresses this issue, but with pessimistic assumptions (no nearby thermally conductive copper to help draw heat away, for instance) and designers often apply that specification using the most conservative assumptions, such as only allowing a minimum temperature increase. While PI-DC cannot replace the IPC-2152 standard as a guideline for thermal considerations, it can give valuable insight into how a design can safely be optimized by studying the voltage drops and current densities of the power delivery system. A design that is optimized for the lowest current density and voltage drop between the sources and all loads will also generate less heat and have less chance of thermal issues.
Another aspect PI-DC analysis addresses is the amount of vias used for power delivery. The problem is quite similar to that of sizing the copper shapes properly: if there are not enough vias, voltage is lost and power is wasted through IR drop, but if too many vias are used, valuable routing real estate is wasted. In particular, if too many vias are used for a particular voltage path, those vias pass through shapes on other layers and reduce their copper cross-section, thereby causing problems for those other voltages. In the same way as correctly dimensioning shapes, analyzing the voltage at the load points allows proper via sizing and/or numbering.
Finally, there is a significant advantage in simulating the final design exactly as it appears physically, to ensure it is optimized. PI-DC simulation provides a final check that connectors and regulators are sized appropriately, in case loads have been dropped or added during the design process, for example.
In the absence of reliable data on the voltage drop through a PCB's various power shapes, ground shapes and vias, a designer is forced to be conservative by using excessive plane shapes, trace sizes and vias, which consume valuable design real estate and increase layers and the design form factor. The Altium PDN Analyzer provides accurate information about a design’s DC power distribution suitability in an easy-to-use and straightforward manner to enable designers to make the most efficient power distribution designs possible.
Not only are the results suitable for final design verification, but they can also be used in the planning stages of a design to architect power delivery as efficiently as possible in advance. PI-DC is an invaluable tool in achieving the most efficient and robust power delivery network possible, the PDN Analyzer makes running that simulation and analysis process straightforward, intuitive and efficient.
Among these and other advantages that the PDN Analyzer brings to your PCB designs, it also delivers the following benefits:
- Product reliability: Helps to ensure the correct performance of individual supplies within the design, in terms of standing voltage levels, voltage stability, and trace heating/damage.
- Improved PCB layout: Provides information that can be applied in creating the most effective use of board space, and allows the easy identification and correction of problematic high current density areas.
- Knowledge: No longer rely on a rule of thumb approach or approximate calculations when considering the layout of DC current paths.
PDN Analyzer simulation
In its most basic form, a board layout that will be subject to PI-DC analysis might be composed of a Voltage Regulator and its load, with interconnecting copper areas of various shapes.
A base circuit example of a power source and load.
The base circuit's PCB layout, with a range of copper shapes and traces connected by layers and vias.
The PDN Analyzer panel interface (Tools » PDN Analyzer) visually emulates a Power Source to Load circuit that incorporates tangible Power and Ground paths – much as shown in the above circuit and also the conceptual block diagram (Fig. 1). The application automatically extracts all physical and electrical information (netlist, devices and layer shapes, etc) from the currently active PCB design, which provides data for the PI-DC simulation engine.
The PDN Analyzer panel interface showing a PI simulation setup for the basic circuit and board layout.
Once the initial parameters have been entered via the interface (source/load voltages and currents, etc) and the simulation has been run, the resulting analysis data is graphically modeled in the PCB editor as a rendered 2D or 3D image.
The Voltage Drop simulation results for the board's PWR net copper (U1 to RL).
The Voltage Drop simulation results for the board's GND net copper(U1 to RL).
The PDN Analyzer PI simulation can be set to show Voltage (IR Drop, above images) or Current Density (below image) results for all applicable board layers.
The Current Density map for both the PWR and GND nets (U1 to RL).
Installation and Licensing
The PDN Analyzer application is added to Altium Designer by installing the PDN Analyzer Extension. Its functionality is enabled with a matching software License.
To install the extension, select the Purchased tab in the Altium Designer's Extension Manager (DXP » Extensions and Updates) and locate the PDN Analyzer powered by CST® icon. Click the icon's button to download and install the extension, and then restart Altium Designer to enable the application.
The extension icon, prior to the PDN Analyzer's installation.
Once installed, the extension will appear under the Extension Manager’s Installed tab. The PDN Analyzer tool is available from the main Tools menu as PDN Analyzer, when a Schematic or PCB project document is open. Note that when the PDN Analyzer is unlicensed, the text associated with the Start Simulation button will indicate that status – see below for license activation steps.
The PDN Analyzer can be licensed using any of Altium's standard License schemes; by activating a On-demand or Standalone license from Altium's License Server, or from an internal network Private License Server.
To locate a license served by Altium's licensing portal, open Altium Designer's License Management page and scan through the Available Licenses list for an On-demand or Standalone PDN Analyzer powered by CST® license entry. Select the desired license and type (On-Demand/Standalone) and click the Use link to activate that license for the PDN Analyzer extension.
When the license is activated, its Assigned Seat Count number will increment and the entry's Used column will include a 'Used by me' entry.