Altium Designer Documentation

Status message

Данная страница доступна на русском языке для версии Altium Designer 20.1: перейти

PDN Analyzerv2_AD

Created: 16.08.2023 | Updated: 18.08.2023

Parent page: Analyzing Your Power Networks

For the latest DC Power Integrity analysis functionality, take a look at Altium's Power Analyzer by Keysight - supported for use in Altium Designer 22.10 and later.

Provided as a downloadable Altium Extension application, the PDN Analyzer powered by CST® (Computer Simulation Technology) integrates directly with Altium Designer to allow PI-DC simulation and analysis of the current PCB project. Since the PDN Analyzer functions within Altium Designer there are no manual data import/export requirements, data conversions or separate applications to be run – simply start the PDN Analyzer from the Schematic or PCB editor, set the desired test parameters and run the simulation. The results are primarily delivered through 2D/3D modeling of the circuit board copper layout, allowing a quick assessment of the results and the opportunity to perform exploratory 'what if' testing of the PCB layout design.

The PDN Analyzer interface shown with the Altium Designer Spirit Level example PCB, and the results of a PI-DC Voltage Drop simulation of its Top layer GND net return for the VCCINT supply.
The PDN Analyzer interface shown with the Altium Designer Spirit Level example PCB, and the results of a PI-DC Voltage Drop simulation of its Top layer GND net return for the VCCINT supply.

► See information on Installing and Licensing the PDN Analyzer extension.

PDN Analyzer Version 2.0

First released as PDN Analyzer version 1.x, the significantly revised PDN Analyzer version 2.0 offers a redesigned interface, new features and more comprehensive results reporting.

The PDN Analyzer 2.0 extension is available for Altium Designer 17.1 and later.

Version 2.0.2

Builds: 306 (for Altium Designer 17.1), 307 (for Altium Designer 18.0) and 309 (for Altium Designer 18.1)


22509 Improved current density uniformity at shape boundaries.
24918 Enabled docking of the PDN Analyzer panel by default.
24934 Reduced the default width of the simulation pane.
24938 Added batch analysis confirmation window.
24972 Allow a config to be opened after its PCB design was renamed.
24993 Improved network rendering for more complex topologies.
25188 Improved Highlight Peak Value "In View" mode behavior.
25189 Aligned Probe X, Y coordinates units with AD units.

Bug Fixes:

24523 Corrected via mesh data for current density.
24636 Fixed bug related to layout changes not propagating to PDNA.
24639 Corrected engineering notation representation of some numerical results.
24649 Corrected Settings form window height.
24662 Corrected HTML report least margins results.
24664 Changed certain HTML report results representation to engineering notation.
24665 Auto-close HTML Report generation window.
24911 Fixed ODB++ export for pads with offset holes.
24913 Fixed bug that reported a VRM's max pin current in the max power column.
24914 Fixed bug in a selection of the bottom item in DC Nets list.
24941 Corrected erroneous HTML report classification of Prepreg layers as Core.
24944 Fixed a bug that limited the number of sequential VRMs to 1.
24971 Fixed a bug that disallowed the changing of a DC Net's nominal voltage.
25044 Corrected a bug that resulted in the omission of top layer data in the Vias tab.
25045 VRM Vout value of 0V is no longer allowed.
25061 Fixed an issue with the propagation of network voltages change to the block diagram.
25064 Corrected linear VRM output voltage in negative supply scenarios.
25071 Corrected erroneous results display on negative supply voltage networks.
25076 Fixed a bug that blocked the ability to disable via current limits.
25078 Fixed an excessive delay that resulted from changing min/max load limits.
25119 Corrected ODB export error related to negative plane thermal reliefs.
25208 Fixed latent display of newly added loads.
25510 Fixed "Index was out of range" bug in HTML report generation.
25568 Corrected the metal resistivity/conductivity calculator in the Settings form.
25714 Fixed bug related to "Object reference not set.." analysis error.
25798 Fixed VRM power dissipation calculation.
26142 Corrected the behavior of the load 5/10% tolerance buttons for negative network voltages.

Version 2.0.1

Builds: 253 (for Altium Designer 17.1) and 254 (for Altium Designer 18.0)

24002 Fixed bug where crash occurred when invoking or creating HTML report.
24003 Fixed simulation error: Can not find VIA vertices.
24004 Fixed a bug that caused a simulation error after tabbing out of a blank device parameter field.
24618 Corrected several minor typing errors in PDNA tooltips.
24543 Fixed unusually slow UI behavior on some installations.

Version 2.0.0

Builds: 244 (for Altium Designer 17.1) and 245 (for Altium Designer 18.0)

Altium has updated the PDN Analyzer extension by significantly enhancing its existing capabilities, adding numerous new features, and resolving issues and limitations in previous releases.

New features in version 2.0:

  • True simultaneous multi-network simulation and linking.
  • Voltage rail net nomination with PCB cross probe.
  • Multi-source support.
  • Intelligent voltage regulator modeling, including sense line support.
  • HTML report generation with image capture.
  • Trace, shape, and via current/density limits.
  • Series element model includes voltage drop parameter for diodes.
  • Visualization features, including:
    • Voltage contour.
    • Current direction indication.
    • Peak value location.
  • Differential voltage probe.
  • Detailed, sortable pin & via results.
  • Automatic network power calculation.

Significant changes:

  • Completely redesigned user interface:
    • More compact and productive layout.
    • Integrated batch analysis and simulation messages tab.
    • Support for increased network complexity.
    • Detailed simulation results tables, including power reporting.
    • Series element includes voltage drop parameter for diodes.
    • Probe now supports differential voltage, current density, and via current.
  • Improved accessibility when docked in Altium Designer.

Resolved issues:

  • Mid-layer polygon planes disappearing when switching layer visibility.
  • High series resistive element values producing unrealistic results.


  1. PDN Analyzer powered by CST® runs on Windows 64-bit systems only.
  2. PDN Analyzer powered by CST does not support embedded components (components placed on an internal layer). Learn more about Designing a PCB with Embedded Components.

► See the PDN Analyzer v2 Example Guide for information on performing power integrity simulations in PDN Analyzer v2.0.

► See information on the previous version of the PDN Analyzer (version 1.x).

The following information on this page provides an overview of the basic electrical and practical principles that apply to Power Integrity Analysis and also includes installation and licensing information for PDN Analyzer v2.0.

Power Integrity Essentials

In essence, the PI-DC (or 'IR drop') problem is fairly straightforward: the resistance embodied in the board's power supply shapes (traces, polygons, planes, etc.,) consumes power and voltage, robbing those from the various loads. As you would expect, the IR issues will increase in complexity with the number of loads on the supply through interaction in the power and ground copper paths.

Figure 1: A basic block diagram of the power and ground shapes, and the applied loads.
Figure 1: A basic block diagram of the power and ground shapes, and the applied loads.

Figure 1 (above) shows a simple block diagram of a circuit's power source and its power and ground shapes (traces and planes) that deliver power to the various loads (memory, microcontrollers, etc.).  Note that all the loads are tied to the same power and ground shapes, and depend on those shapes to provide their operating voltage(s).  In general, we tend to assume that those power and ground shapes have 0Ω resistance, which isn’t necessarily true, and that assumption can cause problems.  Because relatively large currents are often involved, even small resistances in the power and ground shapes can cause significant power consumption (loss) and voltage drops.

Figure 2: 'IR Drop' effects
Figure 2: 'IR Drop' effects

Figure 2 demonstrates an example of the problems that can arise if the resistance of the power and ground shapes are not properly considered.  Even though each shape has a relatively small resistance of only 0.25Ω, they have caused the voltage at the load to drop from 5V to 4.5V.  The designer has to be aware of this drop and ensure it can be accommodated, or change the design to lessen it, to ensure that that the final design will not fail in the field.

The problem, however, seems easy to solve – simply make the power and ground shapes short or large enough to represent an insignificant resistance, using the following relationship: R = ρ * L/A, where:

  • R is the total resistance of a shape (trace or plane)
  • ρ is the resistivity of the material used for the shape (typically copper, ρ ≈ 1.7µΩ-cm)
  • L is the length of the shape
  • A is the cross-section area of the shape (width x thickness)

Put simply, if you make your power and ground shapes short, thick and wide, you will minimize their resistance.

The difficulty with that, however, is that overly large shapes consume valuable routing space and may limit the amount of space for other voltage shapes.  A design which has the properly sized power and ground shapes will be more compact and use fewer layers than one which arbitrarily uses overly large planes or traces.  The intent of PI-DC analysis is to inform a designer that the board design's power and ground shapes are adequate, but not overly large.

Another consideration for IR drop is the fact that the amount of power consumed is I2R – so a small increase in current through a resistance causes a large increase in power consumption.  This can manifest itself as thermal problems where the design heats up significantly because the power and/or ground shapes are not large enough to accommodate the current passing through them.  By ensuring very small IR drop through power and ground shapes, power consumption in those shapes is minimized.

At the extreme, if a shape is resistive enough (very narrow and long) and has sufficient current flowing through it, that shape essentially becomes a 'fuse', thereby melting the copper shape and causing the design to fail – and possibly presenting a dangerous situation.  The IPC-2152 standard for PCB current carrying capacity addresses this issue, but with pessimistic assumptions (no nearby thermally conductive copper to help draw heat away, for instance) and designers often apply that specification using the most conservative assumptions, such as only allowing a minimum temperature increase.  While PI-DC cannot replace the IPC-2152 standard as a guideline for thermal considerations, it can give valuable insight into how a design can safely be optimized by studying the voltage drops and current densities of the power delivery system.  A design that is optimized for the lowest current density and voltage drop between the sources and all loads will also generate less heat and have less chance of thermal issues.

Another aspect PI-DC analysis addresses is the number of vias used for power delivery.  The problem is quite similar to that of sizing the copper shapes properly: if there are not enough vias, voltage is lost and power is wasted through IR drop, but if too many vias are used, valuable routing real estate is wasted.  In particular, if too many vias are used for a particular voltage path, those vias pass through shapes on other layers and reduce their copper cross-section, thereby causing problems for those other voltages.  In the same way as correctly dimensioning shapes, analyzing the voltage at the load points allows proper via sizing and/or numbering.

Finally, there is a significant advantage in simulating the final design exactly as it appears physically, to ensure it is optimized.  PI-DC simulation provides a final check that connectors and regulators are sized appropriately, in case loads have been dropped or added during the design process, for example.

In the absence of reliable data on the voltage drop through a PCB's various power shapes, ground shapes and vias, a designer is forced to be conservative by using excessive plane shapes, trace sizes and vias, which consume valuable design real estate and increase layers and the design form factor.  The Altium PDN Analyzer provides accurate information about a design’s DC power distribution suitability in an easy-to-use and straightforward manner to enable designers to make the most efficient power distribution designs possible.

Not only are the results suitable for final design verification, but they can also be used in the planning stages of a design to architect power delivery as efficiently as possible in advance.  PI-DC is an invaluable tool in achieving the most efficient and robust power delivery network possible, the PDN Analyzer makes running that simulation and analysis process straightforward, intuitive and efficient.

Among these and other advantages that the PDN Analyzer brings to your PCB designs, it also delivers the following benefits:

  • Product reliability: Helps to ensure the correct performance of individual supplies within the design, in terms of standing voltage levels, voltage stability, and trace heating/damage.
  • Improved PCB layout: Provides information that can be applied in creating the most effective use of board space, and allows the easy identification and correction of problematic high current density areas.
  • Knowledge: No longer rely on a rule of thumb approach or approximate calculations when considering the layout of DC current paths.

PDN Analyzer Simulation

In its most very basic form, a board layout that will be subject to PI-DC analysis might be composed of a Voltage Regulator source and its load, with interconnecting copper areas of various shapes and track widths.

A base circuit example of a power source and load.
A base circuit example of a power source and load.

The base circuit's PCB layout, with a range of copper shapes and traces connected by layers and vias.
The base circuit's PCB layout, with a range of copper shapes and traces connected by layers and vias.

The PDN Analyzer panel interface (Tools » PDN Analyzer) visually emulates a Power Source to Load circuit net that incorporates tangible Power and Ground paths – much as shown in the above circuit and also the conceptual block diagram (Fig. 1). The application automatically extracts all physical and electrical information (netlist, devices and layer shapes, etc) from the currently active PCB design, which provides data for the PI-DC simulation engine.

The PDN Analyzer  panel interface showing a PI simulation setup for the basic circuit and board layout.
The PDN Analyzer  panel interface showing a PI simulation setup for the basic circuit and board layout.

Here, the voltage source is the output of U1 (5V between pins 3 and 2), and the load is a specified current through RL (0.1A). Once the initial parameters have been entered via the interface (source/load voltages and currents, etc) and the simulation has been run, the resulting analysis data is graphically modeled in the PCB editor as a rendered 2D or 3D image.

The Voltage Drop simulation results for the board's PWR and GND nets copper (U1 to RL, and RL to U1).The Voltage Drop simulation results for the board's PWR and GND nets copper (U1 to RL, and RL to U1).

The PDN Analyzer PI simulation can be set to show Voltage (IR Drop, above image) or Current Density (below image) results for all applicable board layers.

The Current Density map for both the PWR and GND nets (U1 to RL).

► See the PDN Analyzer example guide for a complete description of using the PDN Analyzer and interpreting its results.

The PDN Analyzer installation includes Altium's SpiritLevel-SL1 PCB reference project with a number of PDN analysis configuration file examples. Access and then unzip the project and samples from the PDNA File » Explore Samples menu option.

Installation and Licensing

The PDN Analyzer application is added to Altium Designer by installing the PDN Analyzer Extension. Its functionality is enabled with a matching software License.


The PDN Analyzer is installed (and updated) from the software's Extensions & Updates view, which is accessed from the User drop-down menu () located at the top right of the Altium Designer GUI.

Select the Purchased tab in the Extensions & Updates view, locate the PDN Analyzer icon and then click its button to download and install the extension. Restart Altium Designer to enable the application.

The extension icon, prior to the PDN Analyzer's installation.
The extension icon, prior to the PDN Analyzer's installation.

A timed Trial License may be offered for the PDN Analyzer. If you wish to use the PDNA on an evaluation basis, follow through the guided steps and confirm the license activation in the License Management view. Otherwise, proceed with a standard license scheme as described below.

Once installed, the extension will appear under the Extension & Updates view’s Installed tab. The PDN Analyzer tool is available from the Altium Designer Tools menu as PDN Analyzer when a Schematic or PCB project document is open. Note that if the PDN Analyzer is unlicensed, a related error message will appear – see below for license activation steps.

Once installed and licensed, the PDN Analyzer icon will also appear under the Updates tab (in Extensions & Updates) when a new version is available for download. Hover the mouse cursor over the icon's download button to see the version information, or select the extension's title to expose more information.

► See the Altium Designer Extensions page for more detailed information about installing and managing extensions.


The PDN Analyzer can be licensed using any of Altium's standard License schemes; by activating an On-demand or Standalone license from Altium's License Server, or from an internal network Private License Server.

► See the License Management page for more information on Altium licensing and types of licenses.

Обнаружили проблему в этом документе? Выделите область и нажмите Ctrl+Enter, чтобы оповестить нас.

Связаться с нами

Связаться с нашими Представительствами напрямую

We're sorry to hear the article wasn't helpful to you.
Could you take a moment to tell us why?
200 characters remaining
Вы сообщаете о проблеме, связанной со следующим выделенным текстом
и/или изображением в активном документе: