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As device switching speeds increase, so too do the demands on the printed circuit board designer and the fabricator. As the length of the signal switching edge becomes shorter than the length of the PCB trace that carries it, the trace has to be treated as part of the circuit. That trace has an impedance, which is referred to as the characteristic impedance (Zo).
The best way to manage the impact of these additional circuit elements is to design the trace routing so that the characteristic impedance is consistent over the length - a technique called controlled impedance routing.
The impedance of the trace routing is defined by the:
In a traditional PCB design, the designer specifies the width/clearance of the trace to satisfy the current/voltage requirements.
In a controlled impedance design the designer specifies the impedance rather than the trace width. Using the built-in Simbeor® impedance calculator, the PCB editor's Layer Stack Manager calculates the trace width needed to deliver the specified impedance.
Impedances are calculated by the Simbeor SFS, a quasi-Static Field Solver. Simbeor SFS is an advanced quasi-static 2D field solver based on Method of Moments, which has been validated by convergence, comparisons, and measurements. The solver meshes dielectric and conductor boundaries and solves corresponding equations to build frequency-dependent RLGC matrices for the Telegraph equations.
Simbeor SFS is not a full-wave solver as this is not needed to evaluate the impedance, delay, or attenuation in PCB interconnects, because of the quasi-TEM nature of the waves propagating there. Such waves can be accurately simulated with RLGC parameters extracted with a quasi-static 2D field solver.
A unique property of the Simbeor SFS solver is that it supports conductor roughness models. Note that it does not support a multi-layered conductor model (plating), and the roughness is common for all conductors. The solver is quasi-static because the solution does not include the high-frequency dispersion that takes place in microstrip lines (higher concentration of fields in a dielectric with higher dielectric constant at high frequencies).
► Learn more about Simberian electromagnetic signal integrity technology
Impedances can be calculated for the following PCB structures:
The trace width required to deliver a specific impedance is calculated as part of the impedance profile, configured in the Impedance tab of the Layer Stack Manager.
When these are correctly configured, the impedance calculator has sufficient information to calculate the:
The calculated values are displayed in the Transmission Line section of the Properties panel, when the Impedance tab is selected in the Layer Stack Manager, as shown below.
From the target impedance and target tolerance, the software calculates the Trace Width. It is not uncommon that the calculated trace width will be a value that cannot be ordered, for example 0.0683mm. The fabricator will advise what material thicknesses are available and what precision they can achieve for trace widths. Then it becomes a process of starting at the desired values, then testing the impact on the calculated impedance values when the dimensions are adjusted to what is available.
To support this process of testing and tuning the settings, the impedance calculators support forward and reverse impedance calculations. The default mode is forward (enter the impedance, the software calculates the width). The icon indicates the calculated variable.
To reverse the calculation and explore different trace widths for the selected layer, type in the new Width (W1) value and press Enter on the keyboard. The calculated values will update to reflect the impact of changing to that width. Click the button to return the calculator to forward calculation mode. Entering a new value into Width (W2) will change the Etch value.
To explore the differential pair transmission line results, nominate the calculated variable - either the Trace Width or Trace Gap - by clicking the appropriate button. Edit the other variable to change the Target Impedance, or alternatively change the Target Impedance to explore the impact on the other variable.
The signal traces on a PCB are fabricated by etching away unwanted copper. Because the etchant starts etching away the copper at the surface, this copper spends more time in contact with the etchant. The result is the finished edges of the trace will have a slope, reducing the cross-sectional area of the finished trace, as shown in the image below.
The area of trace-edge copper lost (on both edges) during etching =
X * Y
The amount of slope is referred to as the Etch Factor, where:
Etch Factor = Y/X
Y = X, then the
Etch Factor = 1
Referring to the image shown in the Properties panel:
The standard definition for Etch Factor is to specify it as the ratio of
trace thickness / amount of over-etching. This gives the following formula:
The downside of this approach is that to specify no over-etching (meaning the trace edges are vertical), you would have to enter a value of
inf (infinite) for the etch factor. To simplify specifying the amount of etch, the formula has been inverted so a value of
0 (zero) can be entered to indicate there is no over-etching.
Another fabrication detail that contributes to the etch factor is the orientation of the copper. PCB traces are formed by etching away unwanted copper from a continuous sheet of copper laminated onto a dielectric substrate. The copper orientation defines the direction the copper projects away from that substrate. You can also think of it as the direction the copper is etched from, either above or below.
The surface of each of the copper layers in a printed circuit board has a degree of roughness. During PCB fabrication the surface of copper layers are treated to increase the roughness, to improve the adhesion between the copper and dielectric layers. This surface roughness becomes a significant contributor to conductor impedance at switching speeds above 10 GB/s. Through extensive research and analysis, industry experts have concluded that the surface roughness can be modeled by a roughness correction coefficient, derived from Surface Roughness and Roughness Factor values.
Roughness settings are available in the Layer Stack Manager mode of the Properties panel. These parameters are used only for conductive layers.
The impedance calculator in the Layer Stack Manager supports single and differential coplanar structures. Create a new impedance profile, then select
Differential-Coplanar from the Impedance Profile Type drop-down list.
Working with coplanar structures:
In a controlled impedance design, the selection of the materials used in the layer stackup is very important.
For example, the most common material used to fabricate PCBs is glass fiber (fiberglass) reinforced epoxy resin, with copper foil bonded onto each side. The tightness of the weave of the glass fiber fabric affects the value and consistency of the dielectric constant Dk (permittivity) and Loss Tangent Df. Surrounding the woven glass fabric is resin - the percentage of resin used is also important in the performance of the material.
There is a large range of glass fiber weaves available. To help ensure the predictability and performance of the glass fiber-based materials used in PCB fabrication, the IPC have a standard for weaves:
IPC standard IPC-4412B: Specification for Finished Fabric Woven from "E" Glass for Printed Boards
As the designer, you can either edit the material properties directly in the Layer Stack Manager, or select materials from the Altium Material Library.
The entire library can be viewed (and added to) in the Altium Material Library dialog (Tools » Material Library).
The materials are organized into usage categories, accessed through a tree structure on the left of the dialog. Below this level, each usage category is broken into functional categories, such as: Conductive layer material, Dielectric layer material and Surface Layer Material; in the PCB layer material category.
New material can added to the library when a specific material category is selected in the tree. Materials defined in an external material library can be loaded (Load button), and user-defined material that has been added in the Altium Material Library dialog can also be saved to a user-library (Save button). Only user-defined material is saved.
Custom properties can be added to material detailed in the library (default and user-defined material). To add a custom property, first select the correct node in the tree on the left to define the material(s) it is to be added to, then click the button to open the Material Library Settings dialog.
The required value can then be added to the selected material in the Altium Material Library dialog, select the row and click the Edit button.
Controlled impedance routing is all about configuring the routing width to deliver the correct impedance, which means the routing width may be different on each signal layer. This is managed by assigning an Impedance Profile instead of a specific routing width when the design rule is configured in the PCB Rules and Constraints Editor (Design » Rules). When this is done the software automatically sets the width to suit the layer.
► Learn more about Controlled Impedance Routing
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