Controlled Impedance Routing

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Parent page: The Routing

With increasing device switching speeds, controlled impedance routing has become a hot topic for the digital designer. This article introduces how you can use the Signal Integrity analysis engine to match component impedances and the controlled impedance routing capabilities in the PCB editor.

There is a saying in engineering circles - there are only two kinds of electronics engineers working in digital design: those who have had signal integrity problems, and those who will. Not so many years ago the term signal integrity was one for the specialist and you only had to deal with it on high speed designs. However, the device switching speeds in those high speed designs are no longer anything special, in fact, they are rapidly becoming the norm. As improving integrated circuit technology drives the size of the transistor down, the speeds at which they can switch goes up. And it is this switching speed that affects the integrity of digital signals.

Thankfully many potential signal integrity issues can be avoided by following good design principals and implementing the design as a controlled impedance board. Achieving this does require specific design tool capabilities - you need analysis tools that can detect nets with potential ringing and reflection issues, and board design tools that allow you to achieve the correct routing impedances. The PCB editor in Altium Designer has these capabilities.

This article will help you understand what causes signal integrity issues and if your board is likely to suffer from them. It will also discuss the two design approaches you must employ to minimizing potential SI issues ­- matching component impedances, and controlled impedance routing.

Controlled Impedance Routing: configuring the routing widths and clearances, as well as the material properties and dimensions, to deliver the required routing impedance(s).

Learn more about High Speed Design in Altium Designer

Do I Need Controlled Impedance Routing?

Do I need to bother with controlled impedance routing, you ask?

In an ideal situation, all of the energy that comes out of a component output pin would be coupled into the connected track on the PCB, flow through the PCB routing to the load input pin at the other end, and be absorbed by that load. If all the energy is not absorbed by the load then the leftover energy can be reflected back into the PCB routing, flowing to the source output pin. This reflected energy can interact with the original signal, adding to and subtracting from it (depending on the polarity of the energy), resulting in ringing. If the ringing is large enough, it will affect the integrity of the signal, resulting in unpredictable, erroneous circuit behavior.

So how do you know if this might occur? If the source pin is able to complete its edge transition before the signal reaches the load pin, the conditions exist for your design to be impacted by reflected energy. A common rule of thumb that is used to determine if SI issues are likely is the "1/3 rise time" rule. This rule states that if the trace is more than 1/3 of a rise time long, reflections (ringing) can occur. If the source pin has a 1 nSec rise time, then a route longer than .33 nSec - which is approximately 2 inches in FR4 - must be considered to be a transmission line, a candidate for signal integrity issues. If your devices have this sort of rise time and you know you will have routing of this sort of length, then you might end up with signal integrity issues on the PCB.

The speed at which the electrical energy can travel along the route is known as the propagation velocity, where:

Vp = speed of light / √ dielectric constant


Time = 1/3 * rise time
eR = 4 (approximation for FR4)
C = 11.811 in/nSec (speed of light, in inches per nanosecond)

√ is the square root symbol

To find the length of route above which the integrity of the signal could become a problem:

LR = Time * Vp
LR = Time * C / eR
LR = .33 * 11.811 / 2
LR = 1.95 in

How Do I Control the Impedances?

How do you avoid the situation where there is energy being reflected back and forth between the source and the load? You avoid it by matching the impedances. Impedance matching ensures that all the energy is coupled from the source into the routing, and then from the routing into the load. Routing the board with regard to the impedance is referred to as controlled impedance routing, or another way of saying it is that a board where impedances have been managed is called a controlled impedance PCB.

There are two distinct elements to achieving impedance matching: the first is matching the components; the second is routing the board to give the required impedance.

Impedance Matching the Components

You cannot achieve a controlled impedance PCB with routing alone. First, you must check, and if necessary, match the impedances of the components.

Ideally, you want to detect nets that could have potential signal integrity issues during the design capture phase so that any additional termination components can be included before the board design process starts. Since output pins are low impedance and input pins are high impedance, it is likely that you will need to add termination components to the design to achieve impedance matching.

You can perform a signal integrity analysis on your design at the schematic capture stage. When you run the Tools » Signal Integrity command the Errors or Warnings dialog will often appear, indicating that not all components have signal integrity models assigned. The Signal Integrity analysis engine will automatically select default models based on the component designators, click Continue to use the defaults or Model Assignments to examine and change the models. You can access the Signal Integrity Model Assignments dialog at any time, via the Model Assignments button in the Signal Integrity panel.

The Signal Integrity analysis engine will use defaults for the required impedance and average track length. It will also use default values for the signal stimulus (the properties of the theoretical signal that is injected). These defaults can be configured once the Signal Integrity panel has opened, via the panel's Menu button » Setup Options command. This command opens the SI Setup Options dialog ( show image), where the Supply Nets can also be configured. If the project includes a PCB, it will be checked for layer stack settings, as well as Supply Nets and Signal Stimulus design rules. Note that the Signal Integrity analysis engine requires power planes for the reference planes, it is not able to use a signal layer covered by a polygon.

The Signal Integrity analysis engine installs as a System Extension. If it is installed it will appear on the Installed list of the Extensions & Updates view, as shown below. If it is not currently installed, click the Configure button to install it.

Extensions add functionality to the design environment, they are managed in the Extensions & Updates view

Learn more about Extending Altium Designer

Analyzing the Design

When the Tools » Signal Integrity command is run the design is analyzed, any potential problem nets are identified in the Signal Integrity panel, as shown below.

Testing the design for potential signal integrity issues during design capture. Testing the design for potential signal integrity issues during design capture.

From the panel, you can perform a reflection analysis on a selected net (or nets). On the left is the analysis results for all nets in the design, select a net and click the  Button to add the selected net(s) to the analysis region of the Signal Integrity panel button (or double-click a net name) to transfer that net to the Net field on the right of the panel, where you can perform a detailed analysis of that net, including:

  • Examining the pins in that net, where you can single-click to cross probe to that pin on the schematic, or double-click to check and configure the model assigned to that pin.
  • Enable one or more theoretical termination options for that net.
  • Perform a Reflection Analysis on the net, producing a set of waveforms showing the behavior at each pin in the net.

The panel allows you to experiment with possible termination configurations and values. Note that the Termination region of the Signal Integrity panel shown in the image above has the Serial Res option enabled. The section of the panel below that shows a series termination resistor. This is where you define the minimum and maximum theoretical series termination resistance values that will be used for the reflection analysis (disable the Suggest checkbox to enter your own values).

Exploring the Results

When the Reflection Waveforms button is clicked an accurate reflection analysis is performed on that net, with the results being presented in a new waveform window (*.SDF).

The waveform window will include:

  • A Chart for each net being analyzed, click the tabs at the bottom of the window to switch between Charts.
  • Each Chart will include a Plot for each pin in that net, showing signal behavior at that pin.

The images below show two graphs of the results at the input pin of the net selected in the previous panel image. The first graph is the input pin in the net without termination; the second graph shows six sweeps, one for the original unterminated net, then five sweeps with the theoretical series termination resistance included at the source pin.

Five passes of the reflection analysis were performed (Sweep Steps option value = 5), with the theoretical termination resistor stepping from Min = 20 ohms to Max = 60 ohms. The five passes (first pass at 20 ohms, last pass at 60 ohms) are listed on the right-hand side of the graph. Clicking on each label highlights that result and displays the theoretical termination resistance value at the bottom right. For this net, a series termination resistance of 40 ohms would produce the graph selected in the image on the right.

The graph on the left shows the reflection analysis of a net with potential signal integrity issues; the graph on the right is the same net with a theoretical series termination resistor of approximately 40 ohms added. Reflection analysis results when the net includes a theoretical series termination resistor, with its value being sweptThe graph on the left shows the reflection analysis of a net with potential signal integrity issues; the graph on the right is the same net with a theoretical series termination resistor of approximately 40 ohms added.

To hide a floating panel, press F4 when the panel is active (the caption bar is colored). Press F4 to restore the display of the panel.

What Determines the Routing Impedance?

The second part of achieving a controlled impedance PCB is to route the board so that the tracks are a defined impedance. There are a number of factors that influence the impedance of your signal routing, including the dimensions of the routes and the properties of the materials used to fabricate the PCB.

Earlier versions of the PCB editor included a simple impedance calculator, with limited support for unusual board structures. This simple impedance calculator had a number of limitations, including requiring return paths to be implemented by plane layers, only supporting symmetrical stripline board structures, and no support for differential impedance calculations.

This release sees the introduction of the Simbeor® electromagnetic Signal Integrity engine from Simberian. Simbeor's model accuracy is validated through the use of advanced algorithms for 3D full wave analysis, benchmarking, and experimental validation. The Simbeor engine supports all modern board structures and materials.

The Simberian site also includes an extensive library of application notes and papers published by Simberian's principal developer, Yuriy Shlepnev, as well as papers written in collaboration with other leading industry and academic researchers.

Configuring the PCB for Controlled Impedance Routing

Controlled Impedance routing is all about configuring the dimensions of the routes and the properties of the board materials to deliver a specific impedance. This is done in the PCB editor's Layer Stack Manager.

To open the Layer Stack Manager select Design » Layer Stack Manager from the menu. The Layer Stack Manager opens in a document editor, in the same way as a schematic sheet, the PCB, and other document types do.

All aspects of layer stack management are performed in the Layer Stack Manager. All aspects of layer stack management are performed in the Layer Stack Manager.

Configuring the Layer Stackup

Main article: Defining the Layer Stack

The copper and dielectric fabrication layers are configured on the Stackup tab of the Layer Stack Manager.

  • Layers are added, removed, and configured in this tab. For a rigid-flex design, layers are also enabled and disabled in this tab.
  • The properties of the currently selected layer can be edited directly in the grid, or in the Properties panel. Click the  Panels button, click to show or hide a workspace panel button at the bottom of the workspace to enable the panel.
  • Right-click in the layer grid or use the Edit » Add Layer commands to add a layer. Adding a copper layer will also add a dielectric layer, when an existing adjacent layer is also a copper layer.
  • If the Stack Symmetry option is enabled in the Board section of the Properties panel, layers are added in matching pairs, centered around the mid-dielectric layer.
  • The layer Material can either be: typed into the selected Material cell; or selected in the Select Material dialog, click the ellipsis button (Ellipsis button, click to select a suitable material from the Select Material dialog) to open it.
  • A surface finish can be added to a copper layer. Use the Add Layer sub-menu to add a Surface Finish layer to the currently selected copper layer, then click the ellipsis button for the new surface finish layer to select the finish type.
  • The selected layer can be moved up or down within the layers of the same type, using either the right-click or Edit menus.
  • The Board section of the Properties panel includes options to enforce Stack Symmetry and Library Compliance, more on these below.
  • The Board section of the Properties panel displays a summary of the currently selected stack (or substack for a multi-stack rigid/flex design).

Layer Stack Considerations

A fundamental requirement for controlling the impedance is to include a signal return path below each signal path. The Simbeor SI engine supports both plane layers, and signal layers covered by a polygon. These return-path layers should be distributed through the board stackup. Ideally, they are arranged so that there is at least one return-path layer adjacent to each signal layer that is carrying controlled impedance routing. The adjacent return-path layer provides the signal return path, and for reasons that will not be covered here, does so regardless of the DC voltage distributed by that plane.

The return path current flowing through the plane will attempt to follow the same physical path as the route on the signal layer, so it is important to avoid introducing discontinuities, such as a split or cutout in the return-path layer underneath any critical signal routing.

As well as selecting a suitable order for signal and plane layers, you also need to define the material properties of each layer, including:

  • Copper thickness
  • Dielectric thickness
  • Dielectric constant

These values, and the routing width, all contribute to the final impedance. Achieving the required impedance then becomes a process of tuning all these values. Keep in mind that possible copper and dielectric thickness values may also be limited, determined by the materials available from your PCB fabricator.

Learn more about possible layer stackups

Defining the Impedance Profiles

Main article: Configuring the Layer Stack for Controlled Impedance Routing

The Simbeor engine is built into the PCB editor's Layer Stack Manager (Design » Layer Stack Manager). To configure the layer stack for controlled impedance routing, switch to the Layer Stack Manager's Impedance tab where you can add and configure an impedance profile.

A 50Ω impedance profile defined for individual nets routed on the top layer, hover the cursor over the image to display the settings for the same profile for layer L3.A 50Ω impedance profile defined for individual nets routed on the top layer, hover the cursor over the image to display the settings for the same profile for layer L3.

Notes on creating and configuring an Impedance Profile:

  1. In the Layer Stack Manager switch to the Impedance tab, as shown above.
  2. Click the Add Impedance Profile button, appears when there are no impedance profiles defined button (or the Plus button, click to add an additional impedance profile button if there is a profile already defined), to add a new profile.
  3. Define the required impedance Type, Target Impedance, and Target Tolerance in the Properties panel. The Description is optional, it will be displayed wherever the Impedance Profile name is displayed.
  4. The grid of layers is divided into 2 regions, the layers in the stackup are displayed on the left, then for each signal layer in the stackup, there is a layer displayed in the Impedance Profile region on the right. Use the layer checkbox in the Profile region to enable impedance calculation for that layer.
  5. Select the enabled layer in the Profile region, all layers in the layer stack will fade except those being used to calculate the impedance for that selected signal layer (as shown in the image above). Edit that layer's reference layer(s) in the Top Ref and Bottom Ref columns. Note that reference layer(s) can be of Type Plane or Signal.
  6. Enable the Impedance Profile checkbox for each other layer that will carry routing at this impedance, and configure the reference plane(s). Hover the cursor over the image above to display the S50 Impedance Profile for layer L3.
  7. If the calculated routing trace width is a value that cannot be ordered, you can tune the width and gap settings.

Configuring the Design Rules

The routing impedance is determined by the width and height of the route, and the properties of the surrounding dielectric materials. Based on the material properties defined in the Layer Stack Manager, the required routing widths are calculated when each impedance profile is created. Depending on the material properties, the width may change as the routing layer is changed. This requirement to changes widths as you change routing layers is automatically managed by the applicable routing design rule configured in the PCB Rules and Constraints Editor (Design » Rules).

For most board designs, there will be a specific set of nets to be routed with a controlled impedance. A common approach is to create a net class or differential pair class that includes these nets, then create a routing rule that targets this class, as shown in the images below.

Normally you manually define the Min, Max, and Preferred Widths, either in the upper constraint settings to apply them to all layers; or individually for each layer in the layer grid. For controlled impedance routing you enable the Use Impedance Profile option instead, then select the required Impedance Profile from the dropdown. When this is done, the Constraints region of the rule will change. The first thing you will notice is that the available layers region will no longer show all signal layers in the board, it will now only show the layers enabled in the selected Impedance Profile. The Preferred Width values (and diff pair gap) will update to reflect the widths (and gaps) calculated for each layer. These Preferred values cannot be edited but the Min and Max values can; set these to suitable smaller/larger values.

Routing Width Design Rule

For single-sided nets, the routing width is defined by the Routing Width design rule.

When you choose to Use an Impedance Profile, the available layers and Preferred Widths are controlled by the selected profile.When you choose to Use an Impedance Profile, the available layers and Preferred Widths are controlled by the selected profile.

Differential Pairs Routing Design Rule

The routing of differential pairs is controlled by the Differential Pair Routing design rule.

For a differential pair, the available layers, the Preferred Width and the Preferred Gap are controlled by the selected profile.For a differential pair, the available layers, the Preferred Width and the Preferred Gap are controlled by the selected profile.

Learn more about Differential Pair Routing

Return Path Design Rule

Breaks or necks in the return path can be detected by the Return Path design rule. The Return Path design rule checks for a continuous signal return path on the designated reference layer(s) above or below the signal(s) targeted by the rule. The return path can be created from fills, regions, and polygon pours placed on the reference signal layer, or it can be a plane layer.

The return path layers are the reference layers defined in the Impedance Profile selected in the Return Path design rule. These layers are checked to ensure the specified Minimum Gap (width beyond the signal edge) exists along the signal's path. Add a new Return Path design rule in the High Speed rule category.

The return path layers are defined in the selected Impedance Profile, the path width (beyond the signal edge) is defined by the Minimum Gap.The return path layers are defined in the selected Impedance Profile, the path width (beyond the signal edge) is defined by the Minimum Gap.

The image below shows return path errors detected for the signal, NetX, with a Minimum Gap setting of 0.1mm. It can be easier to locate Return Path errors by configuring the DRC Violation Display Style to show Violation Details but not the Violation Overlay ( show image), in the Preferences dialog. Doing this highlights the exact locations where the rule has failed, rather than the entire object(s) in violation. 

To avoid detecting small errors, such as the section highlighted in the diagonal track segment in the image above, configure the PCB.Rules.ReturnPathIgnoreArea setting in the Advanced Settings dialog. The default is to ignore areas < 10 sq mils.

Learn more about High Speed Design in Altium Designer

Routing Nets at the Required Impedance

As you route the board and change layers, the software will automatically adjust the track width to the size needed to achieve the specified impedance. This interactive controlled impedance routing greatly simplifies the task of designing a controlled impedance PCB.

Neither the Simbeor impedance calculator integrated into the Layer Stack Manager, or the Signal Integrity Analysis engine include vias in their calculations. Learn more about Defining the Via Types.

Length Tuning the Routes

Two of the core challenges with routing a high-speed design are controlling the impedance of the routes, and matching the lengths of critical nets. Impedance controlled routing ensures that the signal that leaves an output pin is correctly received by the target input pins. Matching the route lengths ensures that timing-critical signals arrive at their target pins at the same time. Tuning and matching route lengths is also an essential ingredient of differential pair routing.

Accordion patterns have been added into the routing to ensure that the differential pairs have matched lengths. Accordion patterns have been added into the routing to ensure that the differential pairs have matched lengths.

The Interactive Length Tuning and Interactive Diff Pair Length Tuning commands (Route menu) provide a dynamic means of optimizing and controlling net or differential pair lengths by allowing variable amplitude wave patterns (accordions) to be inserted, according to the available space, rules, and obstacles in your design.

Learn more about Length Tuning

Testing the Signal Integrity of the Routed Board

In the same way that you tested the nets during design capture using an assumed routing length and routing impedance, once the routing is complete, you should repeat this process on the board to check for potential impedance mismatches and reflection issues. Launch the Signal Integrity command from the PCB editor Tools menu. Since the PCB is part of the project, the material properties and dimensions defined in the Layer Stack Manager and the actual widths of the routes on the board will be used to calculate the impedances used for the signal integrity tests.

Achieving the Specified Impedances

Beyond the iterative dimension tuning process that you go through to achieve the correct impedances, there are other factors that influence the final impedance that will be achieved on your fabricated PCB. These include the consistency and stability of the dielectric material used in the PCB, and also the consistency and quality of the etching process. If you require a controlled impedance PCB, you should discuss this with your PCB fabricator. Some fabricators can advise on track geometries if you supply them with your preferred stackup. Many will also be able to include an impedance test coupon on each panel that they fabricate - this can be used to measure the real impedances achieved on the board.

Additional Reading and Resources

This article gives an introduction to the topic of signal integrity and controlled impedance PCB design. Use the following links to learn more, where you can access resources developed by recognized industry experts.

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